Searched refs:REG (Results 76 - 100 of 296) sorted by relevance

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/linux-master/drivers/ptp/
H A Dptp_clockmatrix.h65 #define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
/linux-master/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser_helper.c50 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_opp.c30 #define REG(reg) \ macro
H A Ddcn201_hubbub.c30 #define REG(reg)\ macro
43 #define REG(reg)\ macro
H A Ddcn201_dccg.c34 #define REG(reg) \ macro
/linux-master/drivers/regulator/
H A Dmc13783-regulator.c244 MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
246 MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
255 MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val),
256 MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val),
275 MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val),
286 MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val),
287 MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val),
288 MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val),
289 MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val),
290 MC13783_GPO_DEFINE(REG, PWGT1SP
[all...]
/linux-master/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c316 #define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 }
319 #define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 }
332 #define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi }
335 #define HOST_HANDLED(REG) { SYS_DESC(REG), .access = NULL }
/linux-master/arch/sparc/include/asm/
H A Dtsb.h77 #define TSB_LOAD_QUAD(TSB, REG) \
78 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
82 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
85 #define TSB_LOAD_TAG_HIGH(TSB, REG) \
86 661: lduwa [TSB] ASI_N, REG; \
89 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
92 #define TSB_LOAD_TAG(TSB, REG) \
93 661: ldxa [TSB] ASI_N, REG; \
96 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.c34 #define REG(reg)\ macro
177 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
178 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
179 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
180 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
181 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
182 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
183 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
184 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
185 gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_
[all...]
H A Ddcn32_hpo_dp_link_encoder.c34 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c34 #define REG(reg)\ macro
73 if (REG(AFMT_CNTL))
76 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
130 if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
137 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
230 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
237 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
244 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
251 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
333 if (REG(DP_MSA_MIS
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/linux-master/drivers/hwmon/
H A Dsmsc47b397.c41 #define REG 0x2e /* The register to read/write */ macro
46 outb(reg, REG);
52 outb(reg, REG);
64 if (!request_muxed_region(REG, 2, DRVNAME))
67 outb(0x55, REG);
73 outb(0xAA, REG);
74 release_region(REG, 2);
152 * REG: 1C/bit, two's complement
174 * REG: count of 90kHz pulses / revolution
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h36 * REG ==> macro to location of register offset
40 dm_read_reg(CTX, REG(reg_name))
43 dm_write_reg(CTX, REG(reg_name), value)
56 REG(reg_name), \
157 generic_reg_get(CTX, REG(reg_name), \
161 generic_reg_get2(CTX, REG(reg_name), \
166 generic_reg_get3(CTX, REG(reg_name), \
172 generic_reg_get4(CTX, REG(reg_name), \
179 generic_reg_get5(CTX, REG(reg_name), \
187 generic_reg_get6(CTX, REG(reg_nam
[all...]
/linux-master/drivers/pinctrl/bcm/
H A Dpinctrl-nsp-gpio.c69 REG, enumerator in enum:base_type
180 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
182 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
219 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
220 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
246 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
247 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
277 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
291 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
292 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OU
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.c33 #define REG(reg)\ macro
140 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
141 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
145 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
146 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
706 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
707 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
708 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
709 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
710 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_
[all...]
H A Ddcn30_dccg.c33 #define REG(reg) \ macro
/linux-master/arch/sparc/net/
H A Dbpf_jit_comp_32.c68 #define SETHI(K, REG) \
69 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
70 #define OR_LO(K, REG) \
71 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
121 #define emit_clear(REG) \
122 do { /* or %g0, %g0, REG */ \
123 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
126 #define emit_set_const(K, REG) \
127 do { /* sethi %hi(K), REG */ \
[all...]
/linux-master/drivers/iio/magnetometer/
H A Dmmc35240.c61 * #define OTP_CONVERT(REG) ((float)((REG) >=32 ? (32 - (REG)) : (REG)) * 0.006
72 #define MMC35240_OTP_CONVERT_Y(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 6)
75 #define MMC35240_OTP_CONVERT_Z(REG) (((REG) >
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dccg.c33 #define REG(reg) \ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_vpg.c35 #define REG(reg)\ macro
H A Ddcn31_afmt.c36 #define REG(reg)\ macro
H A Ddcn31_apg.c35 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_ipp.c30 #define REG(reg) \ macro
/linux-master/arch/mips/kvm/
H A Dtrace.h143 #define KVM_TRACE_COP0(REG, SEL) ((KVM_TRACE_HWR_COP0 << 8) | \
144 ((REG) << 3) | (SEL))
145 #define KVM_TRACE_HWR(REG, SEL) ((KVM_TRACE_HWR_HWR << 8) | \
146 ((REG) << 3) | (SEL))
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_dccg.c34 #define REG(reg) \ macro

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