/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_amdkfd_gfx_v10_3.c | 181 uint32_t __user *wptr, uint32_t wptr_shift, 222 if (wptr) { 223 /* Don't read wptr with get_user because the user 227 * that wptr is GPU-accessible in the queue's VMID via 254 lower_32_bits((uint64_t)wptr)); 256 upper_32_bits((uint64_t)wptr)); 360 uint32_t __user *wptr, struct mm_struct *mm) 367 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 179 hqd_load_v10_3(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument 359 hqd_sdma_load_v10_3(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
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H A D | jpeg_v3_0.c | 373 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 450 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 451 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 453 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | vce_v3_0.c | 153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); 155 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); 157 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); 281 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); 282 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); 288 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); 289 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); 295 WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); 296 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
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H A D | amdgpu_amdkfd_gfx_v7.c | 161 uint32_t __user *wptr, uint32_t wptr_shift, 191 valid_wptr = read_user_wptr(mm, wptr, wptr_val); 240 uint32_t __user *wptr, struct mm_struct *mm) 271 if (read_user_wptr(mm, wptr, data)) 159 kgd_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument 239 kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
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H A D | jpeg_v5_0_0.c | 329 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 406 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 407 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 409 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | amdgpu_amdkfd.h | 266 /* Read user wptr from a specified user address space with page fault 272 #define read_user_wptr(mmptr, wptr, dst) \ 275 if ((mmptr) && (wptr)) { \ 278 valid = !get_user((dst), (wptr)); \ 281 valid = !get_user((dst), (wptr)); \
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H A D | uvd_v7_0.c | 140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 156 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 163 lower_32_bits(ring->wptr)); 166 lower_32_bits(ring->wptr)); 763 adev->uvd.inst[i].ring_enc[0].wptr = 0; 820 ring->wptr = 0; 923 ring->wptr = 0; 1109 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1111 lower_32_bits(ring->wptr)); [all...] |
H A D | amdgpu_amdkfd_gfx_v9.h | 32 uint32_t queue_id, uint32_t __user *wptr,
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H A D | jpeg_v2_0.c | 351 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 429 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 430 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 432 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 652 WARN_ON(ring->wptr % 2 || count % 2);
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H A D | jpeg_v4_0.c | 167 ring->wptr = 0; 406 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 607 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 608 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 610 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | jpeg_v4_0_5.c | 449 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); 534 ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR); 621 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 622 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 624 WREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | amdgpu_ring.c | 44 * GPU is currently reading, and a wptr (write pointer) 48 * wptr. The GPU then starts fetching commands and executes 94 ring->wptr_old = ring->wptr; 137 * Update the wptr (write pointer) to tell the GPU to 146 (ring->wptr & ring->funcs->align_mask); 158 * amdgpu_ring_undo - reset the wptr 162 * Reset the driver's copy of the wptr (all asics). 166 ring->wptr = ring->wptr_old; 467 * - wptr 468 * - driver's copy of wptr [all...] |
H A D | sdma_v3_0.c | 355 * Get the current wptr from the hardware (VI+). 360 u32 wptr; local 364 wptr = *ring->wptr_cpu_addr >> 2; 366 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 369 return wptr; 377 * Write the wptr back to the hardware (VI+). 386 WRITE_ONCE(*wb, ring->wptr << 2); 387 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 391 WRITE_ONCE(*wb, ring->wptr << 2); 393 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << [all...] |
H A D | uvd_v6_0.c | 142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 158 lower_32_bits(ring->wptr)); 161 lower_32_bits(ring->wptr)); 861 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 862 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 868 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 869 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 875 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 876 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1112 WARN_ON(ring->wptr [all...] |
H A D | vpe_v6_1.c | 240 ring->wptr = 0; 242 /* before programing wptr to a less value, need set minor_ptr_update first */ 244 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 245 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 246 /* set minor_ptr_update to 0 after wptr programed */
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H A D | jpeg_v1_0.c | 168 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 416 WARN_ON(ring->wptr % 2 || count % 2); 539 /* initialize wptr */ 540 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 544 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
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H A D | uvd_v3_1.c | 76 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 171 WARN_ON(ring->wptr % 2 || count % 2); 426 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 427 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | uvd_v5_0.c | 88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 446 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 447 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 576 WARN_ON(ring->wptr % 2 || count % 2);
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | uvd_v1_0.c | 70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); 370 ring->wptr = RREG32(UVD_RBC_RB_RPTR); 371 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
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/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a5xx_gpu.h | 87 * preemption, it fills out the record with the useful information (wptr, ring 92 * updating a few registers (often only the wptr). 101 * @wptr: Value of RB_WPTR written by CPU, save/restored by CP 112 uint32_t wptr; member in struct:a5xx_preempt_record
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/linux-master/drivers/watchdog/ |
H A D | i6300esb.c | 98 #define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)
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/linux-master/drivers/scsi/qla2xxx/ |
H A D | qla_sup.c | 552 __le16 *wptr; local 613 wptr = (__force __le16 *)req->ring; 614 cnt = sizeof(*fltl) / sizeof(*wptr); 615 for (chksum = 0; cnt--; wptr++) 616 chksum += le16_to_cpu(*wptr); 674 __le16 *wptr; local 685 wptr = (__force __le16 *)ha->flt; 689 if (le16_to_cpu(*wptr) == 0xffff) 699 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); 700 for (chksum = 0; cnt--; wptr 953 __le16 *wptr = (__force __le16 *)req->ring; local 1046 __le32 *wptr; local 1099 __le16 *wptr; local 1383 __le16 *wptr; local 1426 uint16_t *wptr; local [all...] |
/linux-master/drivers/gpu/drm/amd/include/ |
H A D | kgd_kfd_interface.h | 229 uint32_t queue_id, uint32_t __user *wptr, 238 uint32_t __user *wptr, struct mm_struct *mm);
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/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_packet_manager.c | 31 static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes, argument 34 unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t); 38 *wptr = temp;
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/linux-master/drivers/media/platform/amphion/ |
H A D | vpu_defs.h | 114 u32 wptr; member in struct:vpu_enc_pic_info
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