| /linux-master/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_opp.c | 34 #define FN(reg_name, field_name) \
|
| H A D | dcn201_hubbub.c | 40 #define FN(reg_name, field_name) \
50 #define FN(reg_name, field_name) \
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_panel_cntl.h | 42 #define DCN301_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
43 .field_name = reg_name ## __ ## field_name ## post_fix
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| /linux-master/arch/alpha/lib/ |
| H A D | stacktrace.c | 40 static char reg_name[][4] = { variable
62 printk("\t\t%s / 0x%016lx\n", reg_name[reg], value);
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| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_translate_dce120.c | 51 #define REG(reg_name)\
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
54 #define REGI(reg_name, block, id)\
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
56 mm ## block ## id ## _ ## reg_name
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| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_translate_dcn10.c | 51 #define REG(reg_name)\
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
54 #define REGI(reg_name, block, id)\
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
56 mm ## block ## id ## _ ## reg_name
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.c | 35 #define SR(reg_name)\
36 .reg_name = mm ## reg_name
39 #define SRI(reg_name, block, id)\
40 .reg_name = mm ## block ## id ## _ ## reg_name
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.c | 37 #define SR(reg_name)\
38 .reg_name = mm ## reg_name
41 #define SRI(reg_name, block, id)\
42 .reg_name = mm ## block ## id ## _ ## reg_name
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| /linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr_internal.h | 84 #define CLK_SRI(reg_name, block, inst)\
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
86 mm ## block ## _ ## inst ## _ ## reg_name
120 #define CLK_SF(reg_name, field_name, post_fix)\
121 .field_name = reg_name ## __ ## field_name ## post_fix
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 161 #define SR(reg_name)\
162 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
163 reg ## reg_name
165 #define SRI(reg_name, block, id)\
166 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
169 #define SRI2(reg_name, block, id)\
170 .reg_name
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 149 #define SR(reg_name)\
150 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
151 reg ## reg_name
153 #define SRI(reg_name, block, id)\
154 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 reg ## block ## id ## _ ## reg_name
157 #define SRI2(reg_name, block, id)\
158 .reg_name
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| H A D | hw_translate_dcn315.c | 55 #define REG(reg_name)\
56 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
57 #define SF_HPD(reg_name, field_name, post_fix)\
58 .field_name = reg_name ## __ ## field_name ## post_fix
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| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| H A D | hw_translate_dcn30.c | 60 #define REG(reg_name)\
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\
63 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| H A D | hw_translate_dcn32.c | 53 #define REG(reg_name)\
54 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
55 #define SF_HPD(reg_name, field_name, post_fix)\
56 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_translate_dcn21.c | 55 #define REG(reg_name)\
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
57 #define SF_HPD(reg_name, field_name, post_fix)\
58 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_translate_dcn20.c | 55 #define REG(reg_name)\
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
57 #define SF_HPD(reg_name, field_name, post_fix)\
58 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dio_link_encoder.c | 46 #define FN(reg_name, field_name) \
213 #define AUX_REG_READ(reg_name) \
214 dm_read_reg(CTX, AUX_REG(reg_name))
216 #define AUX_REG_WRITE(reg_name, val) \
217 dm_write_reg(CTX, AUX_REG(reg_name), val)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn321/ |
| H A D | dcn321_dio_link_encoder.c | 51 #define FN(reg_name, field_name) \
57 #define AUX_REG_READ(reg_name) \
58 dm_read_reg(CTX, AUX_REG(reg_name))
60 #define AUX_REG_WRITE(reg_name, val) \
61 dm_write_reg(CTX, AUX_REG(reg_name), val)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 49 #define SR(reg_name)\
50 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
51 mm ## reg_name
57 #define FN(reg_name, field_name) \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 37 #define REG(reg_name) \
38 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
40 #define FN(reg_name, field) \
41 FD(reg_name##__##field)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
55 #define FN(reg_name, field) \
56 FD(reg_name##__##field)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 53 #define REG(reg_name) \
54 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
56 #define FN(reg_name, field) \
57 FD(reg_name##__##field)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dio_link_encoder.c | 53 #define FN(reg_name, field_name) \
59 #define AUX_REG_READ(reg_name) \
60 dm_read_reg(CTX, AUX_REG(reg_name))
62 #define AUX_REG_WRITE(reg_name, val) \
63 dm_write_reg(CTX, AUX_REG(reg_name), val)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 111 #define SR(reg_name)\
112 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
113 mm ## reg_name
115 #define SRI(reg_name, block, id)\
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
120 #define SRII(reg_name, block, id)\
121 .reg_name[i
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 117 #define SR(reg_name)\
118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
119 mm ## reg_name
121 #define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
125 #define SRI2(reg_name, block, id)\
126 .reg_name
[all...] |