/linux-master/drivers/comedi/drivers/ |
H A D | ni_tio.c | 451 u64 ps = 0; local 485 ret = ni_tio_clock_period_ps(counter, clk_src, &ps); 492 if (force_alt_sync || (ps && ps < min_normal_sync_period_ps)) 821 do_div(temp64, 1000); /* ps to ns */
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/linux-master/drivers/dma/ |
H A D | imx-sdma.c | 335 * @ps: peripheral dma status register 361 u32 ps; member in struct:sdma_context_data
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/linux-master/drivers/fpga/ |
H A D | Makefile | 11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_eeprom.c | 186 u16 ps; /* Partial size */ local 213 buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) { 214 ps = min(limit, buf_size); 217 eeprom_buf, ps, read);
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H A D | atom.c | 64 uint32_t *ps, *ws; member in struct:__anon172 228 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 509 ctx->ps[idx] = cpu_to_le32(val); 642 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift, ctx->ps_size - ctx->ps_shift); 1224 int len, ws, ps, ptr; local 1234 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1237 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1240 ectx.ps_shift = ps / 4; 1242 ectx.ps = params; 1264 base, len, ws, ps, pt 1563 uint32_t ps[16]; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/bios/ |
H A D | command_table2.c | 271 struct dig_transmitter_control_ps_allocation_v1_6 ps = { { 0 } }; local 273 ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter); 274 ps.param.action = (uint8_t)cntl->action; 277 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings; 279 ps.param.mode_laneset.digmode = 282 ps.param.lanenum = (uint8_t)cntl->lanes_number; 283 ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel); 284 ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id); 285 ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id; 286 ps 810 struct enable_disp_power_gating_ps_allocation ps = { { 0 } }; local [all...] |
/linux-master/drivers/gpu/drm/amd/include/ |
H A D | kgd_pp_interface.h | 341 void (*print_power_state)(void *handle, void *ps);
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/linux-master/drivers/gpu/drm/amd/pm/inc/ |
H A D | amdgpu_dpm.h | 243 struct amdgpu_ps *ps; member in struct:amdgpu_dpm
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | kv_dpm.c | 360 struct kv_ps *ps = rps->ps_priv; local 362 return ps; 2198 struct kv_ps *ps = kv_get_ps(new_rps); local 2242 ps->need_dfs_bypass = true; 2244 for (i = 0; i < ps->num_levels; i++) { 2245 if (ps->levels[i].sclk < sclk) 2246 ps->levels[i].sclk = sclk; 2250 for (i = 0; i < ps->num_levels; i++) { 2253 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { 2255 ps 2633 kv_patch_boot_state(struct amdgpu_device *adev, struct kv_ps *ps) argument 2647 struct kv_ps *ps = kv_get_ps(rps); local 2674 struct kv_ps *ps = kv_get_ps(rps); local 2706 struct kv_ps *ps; local 2884 struct kv_ps *ps = kv_get_ps(rps); local [all...] |
H A D | legacy_dpm.c | 41 #define amdgpu_dpm_print_power_state(adev, ps) \ 42 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps))) 144 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); 798 struct amdgpu_ps *ps; local 821 ps = &adev->pm.dpm.ps[i]; 822 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 827 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 829 return ps; 831 return ps; 931 struct amdgpu_ps *ps; local [all...] |
H A D | si_dpm.c | 1970 struct si_ps *ps = aps->ps_priv; local 1972 return ps; 3425 struct si_ps *ps = si_get_ps(rps); local 3484 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3485 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3486 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3489 for (i = 0; i < ps->performance_level_count; i++) { 3490 if (ps 3859 struct si_ps *ps = si_get_ps(rps); local 5449 struct si_ps *ps = si_get_ps(amdgpu_state); local 7186 struct si_ps *ps = si_get_ps(rps); local 7275 struct si_ps *ps; local 7532 struct si_ps *ps = si_get_ps(rps); local 7922 struct si_ps *ps = si_get_ps(rps); local 8012 struct si_ps *ps = si_get_ps(rps); local [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/ |
H A D | amd_powerplay.c | 617 if (!hwmgr || !hwmgr->pm_en || !hwmgr->ps) 624 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | pp_psm.c | 53 hwmgr->ps = kcalloc(table_entries, size, GFP_KERNEL); 54 if (hwmgr->ps == NULL) 59 kfree(hwmgr->ps); 60 hwmgr->ps = NULL; 67 kfree(hwmgr->ps); 69 hwmgr->ps = NULL; 73 state = hwmgr->ps; 80 kfree(hwmgr->ps); 83 hwmgr->ps = NULL; 108 if (!hwmgr->ps) [all...] |
H A D | processpptables.c | 677 struct pp_power_state *ps, 683 ps->classification.ui_label = (le16_to_cpu(pnon_clock_info->usClassification) & 685 ps->classification.flags = make_classification_flags(hwmgr, 689 ps->classification.temporary_state = false; 690 ps->classification.to_be_deleted = false; 694 ps->validation.singleDisplayOnly = (0 != tmp); 699 ps->validation.disallowOnDC = (0 != tmp); 701 ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & 705 ps->pcie.lanes = 0; 707 ps 676 init_non_clock_fields(struct pp_hwmgr *hwmgr, struct pp_power_state *ps, uint8_t version, const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info) argument 883 pp_tables_get_entry(struct pp_hwmgr *hwmgr, unsigned long entry_index, struct pp_power_state *ps, pp_tables_hw_clock_info_callback func) argument [all...] |
H A D | processpptables.h | 44 struct pp_power_state *ps,
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H A D | smu10_hwmgr.c | 921 unsigned long entry, struct pp_power_state *ps) 926 ps->hardware.magic = SMU10_Magic; 928 smu10_ps = cast_smu10_ps(&(ps->hardware)); 930 result = pp_tables_get_entry(hwmgr, entry, ps, 933 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; 934 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; 1135 const struct smu10_power_state *ps = cast_const_smu10_ps(state); local 1137 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); 1138 clock_info->max_eng_clk = ps 920 smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, unsigned long entry, struct pp_power_state *ps) argument [all...] |
H A D | smu7_hwmgr.c | 3488 struct pp_power_state *ps; local 3494 ps = hwmgr->request_ps; 3496 if (ps == NULL) 3499 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3510 struct pp_power_state *ps; local 3516 ps = hwmgr->request_ps; 3518 if (ps == NULL) 3521 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3534 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps; local 3567 ps 3692 struct smu7_power_state *ps; local 3795 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state); local 3837 struct smu7_power_state *ps; local 5102 struct pp_power_state *ps; local 5144 struct pp_power_state *ps; local 5706 const struct smu7_power_state *ps; local [all...] |
H A D | smu8_hwmgr.c | 1341 struct pp_power_state *ps; local 1347 ps = hwmgr->request_ps; 1349 if (ps == NULL) 1352 smu8_ps = cast_smu8_power_state(&ps->hardware); 1415 unsigned long entry, struct pp_power_state *ps) 1420 ps->hardware.magic = smu8_magic; 1422 smu8_ps = cast_smu8_power_state(&(ps->hardware)); 1424 result = pp_tables_get_entry(hwmgr, entry, ps, 1427 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; 1428 smu8_ps->uvd_clocks.dclk = ps 1414 smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, unsigned long entry, struct pp_power_state *ps) argument 1600 const struct smu8_power_state *ps; local 1638 const struct smu8_power_state *ps = cast_const_smu8_power_state(state); local [all...] |
H A D | vega10_hwmgr.c | 3857 struct pp_power_state *ps; local 3863 ps = hwmgr->request_ps; 3865 if (ps == NULL) 3868 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3879 struct pp_power_state *ps; local 3885 ps = hwmgr->request_ps; 3887 if (ps == NULL) 3890 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5122 struct pp_power_state *ps; local 5125 ps 5173 struct pp_power_state *ps; local 5409 struct pp_power_state *ps = hwmgr->request_ps; local [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/ |
H A D | hwmgr.h | 781 struct pp_power_state *ps; member in struct:pp_hwmgr
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/linux-master/drivers/gpu/drm/bridge/ |
H A D | nwl-dsi.c | 188 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) argument 192 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
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H A D | samsung-dsim.c | 225 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)
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H A D | tc358768.c | 639 static u32 tc358768_ps_to_ns(u32 ps) argument 641 return ps / 1000; 908 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps,
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/linux-master/drivers/gpu/drm/i915/gt/uc/ |
H A D | intel_guc_submission.c | 483 struct parent_scratch *ps = __get_parent_scratch(ce); local 485 return &ps->descs.pdesc; 491 struct parent_scratch *ps = __get_parent_scratch(ce); local 493 return &ps->descs.wq_desc; 2588 struct parent_scratch *ps = __get_parent_scratch(ce); local 2591 ps->go.semaphore = 0; 2593 ps->join[i].semaphore = 0;
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/linux-master/drivers/gpu/drm/i915/selftests/ |
H A D | i915_request.c | 1637 snprintf(name, sizeof(name), "%ps", *fn); 2732 struct perf_series *ps = arg; local 2737 GEM_BUG_ON(!ps->nengines); 2741 rq = i915_request_create(ps->ce[idx]); 2756 if (++idx == ps->nengines) 2765 struct perf_series *ps = arg; local 2771 GEM_BUG_ON(!ps->nengines); 2775 rq = i915_request_create(ps->ce[idx]); 2791 if (++idx == ps->nengines) 2801 struct perf_series *ps local 2836 struct perf_series *ps; local [all...] |