/linux-master/drivers/gpu/drm/exynos/ |
H A D | exynos7_drm_decon.c | 319 * switching which is based on plane size is not recommended as 320 * plane size varies a lot towards the end of the screen and rapid 381 struct exynos_drm_plane *plane) 384 to_exynos_plane_state(plane->base.state); 391 unsigned int win = plane->index; 479 struct exynos_drm_plane *plane) 482 unsigned int win = plane->index; 380 decon_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) argument 478 decon_disable_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) argument
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H A D | exynos_drm_vidi.c | 112 struct exynos_drm_plane *plane) 114 struct drm_plane_state *state = plane->base.state; 111 vidi_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) argument
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/linux-master/drivers/gpu/drm/gma500/ |
H A D | psb_intel_display.c | 199 /* Set up the display plane register */ 294 /* Flush the plane changes */ 503 gma_crtc->plane = pipe; 517 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); 518 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
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H A D | psb_intel_drv.h | 140 int plane; member in struct:gma_crtc
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/linux-master/drivers/gpu/drm/msm/ |
H A D | msm_drv.h | 287 struct msm_gem_address_space *aspace, int plane); 288 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
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/linux-master/drivers/gpu/drm/ast/ |
H A D | ast_drv.h | 144 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane) argument 146 return container_of(plane, struct ast_plane, base); 389 /* Last known format of primary plane */
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/linux-master/drivers/gpu/drm/atmel-hlcdc/ |
H A D | atmel_hlcdc_dc.h | 256 * A layer can be a DRM plane of a post processing layer used to render 270 * @base: base DRM plane structure 404 void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);
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/linux-master/drivers/gpu/drm/aspeed/ |
H A D | aspeed_gfx_crtc.c | 168 struct drm_framebuffer *fb = pipe->plane.state->fb;
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/linux-master/drivers/media/platform/qcom/camss/ |
H A D | camss-vfe-4-1.c | 290 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, argument 299 if (plane == 1) 305 u8 plane, u32 enable) 312 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 303 vfe_wm_line_based(struct vfe_device *vfe, u32 wm, struct v4l2_pix_format_mplane *pix, u8 plane, u32 enable) argument
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H A D | camss-vfe-4-7.c | 370 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, argument 380 if (plane == 1) 391 *bytesperline = pix->plane_fmt[plane].bytesperline; 398 u8 plane, u32 enable) 405 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 396 vfe_wm_line_based(struct vfe_device *vfe, u32 wm, struct v4l2_pix_format_mplane *pix, u8 plane, u32 enable) argument
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H A D | camss-vfe-4-8.c | 343 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, argument 353 if (plane == 1) 364 *bytesperline = pix->plane_fmt[plane].bytesperline; 371 u8 plane, u32 enable) 378 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 369 vfe_wm_line_based(struct vfe_device *vfe, u32 wm, struct v4l2_pix_format_mplane *pix, u8 plane, u32 enable) argument
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/linux-master/drivers/gpu/drm/nouveau/dispnv50/ |
H A D | disp.c | 2153 struct drm_plane *plane; local 2156 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2157 struct nv50_wndw *wndw = nv50_wndw(plane); 2172 struct drm_plane *plane; local 2212 /* Disable plane(s). */ 2213 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2215 struct nv50_wndw *wndw = nv50_wndw(plane); 2217 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2341 /* Update plane(s). */ 2342 for_each_new_plane_in_state(state, plane, new_plane_stat 2428 struct drm_plane *plane; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_color.c | 61 * plane cases correctly with clever management of the DC interface in DM. 597 * since we don't have any plane level adjustments using it. 787 * DRM plane gamma LUT or TF means we are linearizing color 810 * @plane_state: the DRM plane state 891 * With no plane level color management properties we're free to use any 902 * For supporting both plane level color management and CRTC level color 1111 /* If we don't have plane degamma LUT nor TF to set on DC, we have 1165 drm_dbg_kms(plane_state->plane->dev, 1166 "setting plane %d shaper LUT failed.\n", 1167 plane_state->plane [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_hw_sequencer.c | 387 /* Determine the overscan color based on the top-most (desktop) plane's context */ 566 struct dc_plane_state *plane = pipe_ctx->plane_state; local 575 if (!plane || !stream) 582 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; 705 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; 910 /* Determine the overscan color based on the bottom-most plane's context */
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/linux-master/drivers/gpu/drm/vc4/ |
H A D | vc4_crtc.c | 843 * we can actually update the plane's address to point to it. 850 struct drm_plane *plane = crtc->primary; local 852 vc4_plane_async_set_fb(plane, flip_state->fb); 948 struct drm_plane *plane = crtc->primary; local 968 flip_state->old_fb = plane->state->fb; 974 /* Immediately update the plane's legacy fb pointer, so that later 978 drm_atomic_set_fb_for_plane(plane->state, fb); 1009 * plane is later updated through the non-async path. 1304 * @primary_plane: Primary plane for CRTC 1373 * requirement of the plane configuratio [all...] |
H A D | vc4_drv.h | 400 /* Offset where the plane's dlist was last stored in the 405 /* Clipped coordinates of the plane on the display. */ 412 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */ 417 /* Offset to start scanning out from the start of the plane's 425 /* Set when the plane has per-pixel alpha content or does not cover 436 /* Load of this plane on the HVS block. The load is expressed in HVS 441 /* Memory bandwidth needed for this plane. This is expressed in 1027 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 1029 void vc4_plane_async_set_fb(struct drm_plane *plane,
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/linux-master/drivers/media/platform/ti/vpe/ |
H A D | vpe.c | 65 /* used as plane indices */ 155 u8 vb_part; /* plane index for co-panar formats */ 230 /* vpdma format info for each plane */ 1039 int plane = fmt->coplanar ? p_data->vb_part : 0; local 1042 vpdma_fmt = fmt->vpdma_fmt[plane]; 1044 * If we are using a single plane buffer and 1047 if (pix->num_planes == 1 && plane) { 1052 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane); 1106 int plane = fmt->coplanar ? p_data->vb_part : 0; local 1108 vpdma_fmt = fmt->vpdma_fmt[plane]; [all...] |
/linux-master/drivers/gpu/drm/i915/gvt/ |
H A D | cmd_parser.c | 1268 int plane; member in struct:mi_display_flip_command_info 1281 int plane; member in struct:plane_code_mapping 1309 info->plane = gen8_plane_code[v].plane; 1316 if (info->plane == PLANE_A) { 1320 } else if (info->plane == PLANE_B) { 1339 u32 plane = (dword0 & GENMASK(12, 8)) >> 8; local 1341 info->plane = PRIMARY_PLANE; 1343 switch (plane) { 1360 info->plane [all...] |
/linux-master/drivers/media/platform/samsung/exynos4-is/ |
H A D | fimc-is-param.h | 482 u32 plane; member in struct:param_dma_input 507 u32 plane; member in struct:param_dma_output
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/linux-master/drivers/gpu/drm/gud/ |
H A D | gud_drv.c | 291 ret = drm_plane_create_rotation_property(&gdrm->pipe.plane, 599 drm_plane_enable_fb_damage_clips(&gdrm->pipe.plane);
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H A D | gud_pipe.c | 454 struct drm_plane_state *old_plane_state = pipe->plane.state; 570 struct drm_plane_state *state = pipe->plane.state;
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/linux-master/drivers/gpu/drm/sun4i/ |
H A D | sun8i_mixer.c | 279 "Couldn't initialize overlay plane\n"); 283 planes[i] = &layer->plane; 291 dev_err(drm->dev, "Couldn't initialize %s plane\n", 296 planes[mixer->cfg->vi_num + i] = &layer->plane; 512 * Set fill color of bottom plane to black. Generally not needed 513 * except when VI plane is at bottom (zpos = 0) and enabled.
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/linux-master/drivers/gpu/drm/imx/lcdc/ |
H A D | imx-lcdc.c | 141 struct drm_plane_state *new_state = pipe->plane.state; 301 struct drm_plane_state *new_state = pipe->plane.state;
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/linux-master/drivers/media/platform/cadence/ |
H A D | cdns-csi2rx.c | 32 #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4))
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/linux-master/drivers/gpu/drm/xen/ |
H A D | xen_drm_front_kms.c | 183 &pipe->plane);
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