Searched refs:reg (Results 276 - 300 of 1755) sorted by relevance

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/freebsd-11-stable/sys/arm/samsung/exynos/
H A Dexynos5_mct.c87 int reg, i; local
101 reg = bus_space_read_4(sc->bst, sc->bsh, MCT_CTRL);
102 reg |= MCT_CTRL_START;
103 bus_space_write_4(sc->bst, sc->bsh, MCT_CTRL, reg);
109 reg = bus_space_read_4(sc->bst, sc->bsh, MCT_WRITE_STAT);
110 if (reg & mask) {
/freebsd-11-stable/sys/arm/amlogic/aml8726/
H A Daml8726_pinctrl.c84 #define MUX_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
85 #define MUX_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
87 #define PUD_WRITE_4(sc, reg, val) bus_write_4((sc)->res[1], reg, (val))
88 #define PUD_READ_4(sc, reg) bus_read_4((sc)->res[1], reg)
90 #define PEN_WRITE_4(sc, reg, val) bus_write_4((sc)->res[2], reg, (va
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/freebsd-11-stable/sys/dev/an/
H A Dif_anreg.h48 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->port_res, reg, val)
50 #define CSR_READ_2(sc, reg) bus_read_2(sc->port_res, reg)
52 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->port_res, reg, val)
54 #define CSR_READ_1(sc, reg) bus_read_1(sc->port_res, reg)
59 #define CSR_MEM_WRITE_2(sc, reg, val) bus_write_2(sc->mem_res, reg, va
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/freebsd-11-stable/sys/mips/atheros/
H A Duart_dev_ar933x.c50 #define ar933x_getreg(bas, reg) \
51 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
52 #define ar933x_setreg(bas, reg, value) \
53 bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
226 uint32_t reg; local
237 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
238 reg &= ~AR933X_UART_CS_HOST_INT_EN;
239 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
370 uint32_t reg; local
387 reg
398 uint32_t reg; local
716 uint32_t reg; local
730 uint32_t reg; local
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/freebsd-11-stable/sys/dev/hwpmc/
H A Dhwpmc_armv7.c64 uint32_t reg; local
66 reg = (1 << pmc);
67 cp15_pminten_set(reg);
76 uint32_t reg; local
78 reg = (1 << pmc);
79 cp15_pminten_clr(reg);
88 uint32_t reg; local
90 reg = (1 << pmc);
91 cp15_pmcnten_set(reg);
100 uint32_t reg; local
120 armv7_pmcn_write(unsigned int pmc, uint32_t reg) argument
304 int reg; local
459 int reg; local
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/freebsd-11-stable/sys/dev/scc/
H A Dscc_bfe.h48 #define scc_regofs(bas, reg) ((reg) << (bas)->regshft)
50 #define scc_getreg(bas, reg) \
51 bus_space_read_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg))
52 #define scc_setreg(bas, reg, value) \
53 bus_space_write_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg), value)
/freebsd-11-stable/sys/dev/sound/macio/
H A Ddavbus.c63 struct resource *reg; member in struct:davbus_softc
182 bus_read_4(d->reg, DAVBUS_CODEC_STATUS)));
204 burgundy_write_locked(struct davbus_softc *d, u_int reg, u_int val) argument
208 size = (reg & 0x00FF0000) >> 16;
209 addr = (reg & 0x0000FF00) >> 8;
210 offset = reg & 0xFF;
218 bus_write_4(d->reg, DAVBUS_CODEC_CTRL, data);
220 while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) &
349 bus_read_4(d->reg, DAVBUS_CODEC_STATUS)));
377 screamer_write_locked(struct davbus_softc *d, u_int reg, u_in argument
580 u_int reg, status, mask; local
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/freebsd-11-stable/sys/arm/freescale/imx/
H A Dimx6_src.c75 uint32_t reg; local
81 reg = RD4(src_sc, SRC_SCR);
82 reg |= SW_IPU1_RST;
83 WR4(src_sc, SRC_SCR, reg);
86 reg = RD4(src_sc, SRC_SCR);
87 if (reg & SW_IPU1_RST)
/freebsd-11-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_machdep.c100 uint32_t reg; local
105 reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);
106 reg &= PMC_SCRATCH0_MODE_MASK;
108 reg | PMC_SCRATCH0_MODE_BOOTLOADER); /* boot to bootloader */
111 reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);
114 bus_space_write_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG, reg | 0x10);
/freebsd-11-stable/sys/dev/liquidio/base/
H A Dlio_device.h811 lio_read_pci_cfg(struct octeon_device *oct, uint32_t reg) argument
814 return (pci_read_config(oct->device, reg, 4));
818 lio_write_pci_cfg(struct octeon_device *oct, uint32_t reg, uint32_t value) argument
821 pci_write_config(oct->device, reg, value, 4);
825 lio_read_csr8(struct octeon_device *oct, uint32_t reg) argument
829 oct->mem_bus_space[0].handle, reg));
833 lio_write_csr8(struct octeon_device *oct, uint32_t reg, uint8_t val) argument
837 oct->mem_bus_space[0].handle, reg, val);
841 lio_read_csr16(struct octeon_device *oct, uint32_t reg) argument
845 oct->mem_bus_space[0].handle, reg));
849 lio_write_csr16(struct octeon_device *oct, uint32_t reg, uint16_t val) argument
857 lio_read_csr32(struct octeon_device *oct, uint32_t reg) argument
865 lio_write_csr32(struct octeon_device *oct, uint32_t reg, uint32_t val) argument
873 lio_read_csr64(struct octeon_device *oct, uint32_t reg) argument
886 lio_write_csr64(struct octeon_device *oct, uint32_t reg, uint64_t val) argument
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/freebsd-11-stable/stand/powerpc/ofw/
H A Dmain.c73 cell_t reg[24]; local
80 sz = OF_getprop(memoryp, "reg", &reg, sizeof(reg));
81 sz /= sizeof(reg[0]);
85 memsz += (uint64_t)reg[i + acells] << 32;
86 memsz += reg[i + acells + scells - 1];
/freebsd-11-stable/contrib/gcc/config/
H A Ddarwin.c30 #include "hard-reg-set.h"
502 machopic_indirect_data_reference (rtx orig, rtx reg) argument
517 rtx hi_reg = (no_new_pseudos ? reg : gen_reg_rtx (Pmode));
519 emit_insn (gen_macho_low (reg, hi_reg, orig));
524 return reg;
534 rtx hi_sum_reg = (no_new_pseudos ? reg : gen_reg_rtx (Pmode));
536 gcc_assert (reg);
541 emit_insn (gen_rtx_SET (Pmode, reg,
544 orig = reg;
547 gcc_assert (reg);
659 machopic_legitimize_pic_address(rtx orig, enum machine_mode mode, rtx reg) argument
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/freebsd-11-stable/contrib/gcc/config/arm/
H A Dpr-support.c112 _uw reg; local
124 &reg);
126 &reg);
138 _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, &reg);
140 reg -= offset;
142 reg += offset;
143 _Unwind_VRS_Set (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, &reg);
171 _Unwind_VRS_Get (context, _UVRSC_CORE, op, _UVRSD_UINT32, &reg);
172 _Unwind_VRS_Set (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, &reg);
209 &reg);
[all...]
/freebsd-11-stable/sys/mips/rt305x/
H A Drt305x_ehci.c85 uint32_t reg; local
90 reg = rt305x_sysctl_get(SYSCTL_SYSCFG1);
91 reg |= SYSCTL_SYSCFG1_USB0_HOST_MODE;
92 rt305x_sysctl_set(SYSCTL_SYSCFG1, reg);
94 reg = rt305x_sysctl_get(SYSCTL_CLKCFG1);
95 reg |= SYSCTL_CLKCFG1_UPHY0_CLK_EN;
97 reg |= SYSCTL_CLKCFG1_UPHY1_CLK_EN;
99 rt305x_sysctl_set(SYSCTL_CLKCFG1, reg);
101 reg = rt305x_sysctl_get(SYSCTL_RSTCTRL);
102 reg |
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H A Drt305x_ohci.c85 uint32_t reg; local
90 reg = rt305x_sysctl_get(SYSCTL_SYSCFG1);
91 reg |= SYSCTL_SYSCFG1_USB0_HOST_MODE;
92 rt305x_sysctl_set(SYSCTL_SYSCFG1, reg);
94 reg = rt305x_sysctl_get(SYSCTL_CLKCFG1);
95 reg |= SYSCTL_CLKCFG1_UPHY0_CLK_EN;
97 reg |= SYSCTL_CLKCFG1_UPHY1_CLK_EN;
99 rt305x_sysctl_set(SYSCTL_CLKCFG1, reg);
101 reg = rt305x_sysctl_get(SYSCTL_RSTCTRL);
102 reg |
[all...]
/freebsd-11-stable/sys/dev/iicbus/
H A Ds35390a.c156 s390rtc_read(device_t dev, uint8_t reg, uint8_t *buf, size_t len) argument
161 .slave = sc->sc_addr | reg,
182 s390rtc_write(device_t dev, uint8_t reg, uint8_t *buf, size_t len) argument
187 .slave = sc->sc_addr | reg,
230 uint8_t reg; local
236 error = s390rtc_read(dev, S390_STATUS1, &reg, 1);
242 if (reg & (S390_ST1_POC | S390_ST1_BLD)) {
243 reg |= S390_ST1_24H | S390_ST1_RESET;
244 error = s390rtc_write(dev, S390_STATUS1, &reg, 1);
253 error = s390rtc_read(dev, S390_STATUS2, &reg,
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/freebsd-11-stable/sys/dev/tws/
H A Dtws_hdm.c85 u_int64_t reg; local
101 reg = (((u_int64_t)regh) << 32) | regl;
102 TWS_TRACE_DEBUG(sc, "host outbound cleanup",reg, regl);
417 u_int32_t reg; local
419 reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);
420 if ( reg & TWS_BIT13 )
449 u_int32_t reg; local
452 reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);
453 reg = reg | TWS_BIT
460 u_int32_t reg; local
472 u_int32_t reg; local
496 u_int32_t reg; local
[all...]
/freebsd-11-stable/tools/tools/ath/athdecode/
H A Dmain.c114 switch (r->reg) {
192 fprintf(fd, "mark #%u value %u/0x%x", r->reg, r->val, r->val);
354 findreg(int reg) argument
361 if (dr->addr == reg &&
383 dr = findreg(r->reg);
385 snprintf(buf, sizeof (buf), "AR_%s (0x%x)", dr->name, r->reg);
387 } else if (AR_KEYTABLE(0) <= r->reg && r->reg < AR_KEYTABLE(128)) {
389 ((r->reg - AR_KEYTABLE_0) >> 2) & 7,
390 (r->reg
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/freebsd-11-stable/sys/arm/xilinx/
H A Dzy7_slcr.c262 uint32_t reg; local
273 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
274 reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK);
275 reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);
276 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
290 uint32_t reg; local
299 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
300 source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >>
318 uint32_t reg; local
363 reg
385 uint32_t reg; local
486 uint32_t reg; local
503 uint32_t reg; local
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/freebsd-11-stable/sys/dev/urtwn/
H A Dif_urtwn.c461 uint16_t reg; member in struct:wme_to_queue
1667 uint32_t reg[R92C_MAX_CHAINS], val; local
1669 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1671 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1674 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
1678 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1683 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
1718 uint32_t reg; local
1725 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1726 reg
1756 uint8_t reg; local
1807 uint8_t msk, off, reg; local
1857 uint32_t reg; local
1892 uint32_t reg; local
2430 uint32_t reg; local
2505 uint8_t reg; local
2532 uint8_t reg; local
2573 uint32_t reg; local
3367 uint32_t reg; local
3473 uint32_t reg; local
3558 uint32_t reg; local
3686 uint8_t reg; local
3846 uint16_t reg; local
3866 uint16_t reg; local
3876 uint32_t reg; local
3912 uint32_t reg; local
4032 uint32_t reg; local
4195 uint32_t reg; local
4313 uint32_t reg, type; local
4416 uint8_t reg; local
4513 uint32_t reg; local
4759 uint32_t reg; local
4772 uint32_t reg; local
5108 uint32_t reg; local
5315 uint32_t reg; local
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/freebsd-11-stable/contrib/binutils/gas/config/
H A Dtc-cr16.c312 static reg
315 const reg_entry *reg; local
317 reg = (const reg_entry *) hash_find (reg_hash, reg_name);
319 if (reg != NULL)
320 return reg->value.reg_val;
326 static reg
329 const reg_entry *reg; local
332 /* Add '(' and ')' to the reg pair, if its not present. */
338 reg = (const reg_entry *) hash_find (regp_hash, tmp_rp);
341 reg
354 const reg_entry *reg; local
369 const reg_entry *reg; local
758 const reg_entry * reg; local
1007 const reg_entry *reg; local
1481 const reg_entry *reg; local
1520 const reg_entry *reg; local
1567 const reg_entry *reg; local
1605 const reg_entry *reg; local
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/freebsd-11-stable/sys/dev/drm/
H A Dvia_drv.h113 #define VIA_READ(reg) DRM_READ32(VIA_BASE, reg)
114 #define VIA_WRITE(reg,val) DRM_WRITE32(VIA_BASE, reg, val)
115 #define VIA_READ8(reg) DRM_READ8(VIA_BASE, reg)
116 #define VIA_WRITE8(reg,val) DRM_WRITE8(VIA_BASE, reg, val)
/freebsd-11-stable/lib/libc/sparc64/sys/
H A D__sparc_utrap_private.h54 u_long __emul_fetch_reg(struct utrapframe *uf, int reg);
55 void __emul_store_reg(struct utrapframe *uf, int reg, u_long val);
/freebsd-11-stable/lib/libthread_db/arch/amd64/
H A Dlibpthread_md.c39 pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)
66 pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)
114 pt_reg_sstep(struct reg *reg, int step) argument
118 old = reg->r_rflags;
120 reg->r_rflags |= 0x0100;
122 reg->r_rflags &= ~0x0100;
123 return (old != reg->r_rflags); /* changed ? */
/freebsd-11-stable/sys/dev/mii/
H A Dnsphyter.c223 int reg, i; local
226 reg = BMCR_RESET;
228 reg = BMCR_RESET | BMCR_ISO;
229 PHY_WRITE(sc, MII_BMCR, reg);
251 reg = PHY_READ(sc, MII_BMCR);
252 if (reg != 0 && (reg & BMCR_RESET) == 0)
260 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

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