1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Cavium, Inc. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33/*$FreeBSD: stable/11/sys/dev/liquidio/base/lio_device.h 325618 2017-11-09 19:52:56Z sbruno $*/ 34 35/* 36 * \brief Host Driver: This file defines the octeon device structure. 37 */ 38 39#ifndef _LIO_DEVICE_H_ 40#define _LIO_DEVICE_H_ 41 42#include <sys/endian.h> /* for BYTE_ORDER */ 43 44/* PCI VendorId Device Id */ 45#define LIO_CN23XX_PF_PCIID 0x9702177d 46/* 47 * Driver identifies chips by these Ids, created by clubbing together 48 * DeviceId+RevisionId; Where Revision Id is not used to distinguish 49 * between chips, a value of 0 is used for revision id. 50 */ 51#define LIO_CN23XX_PF_VID 0x9702 52#define LIO_CN2350_10G_SUBDEVICE 0x03 53#define LIO_CN2350_10G_SUBDEVICE1 0x04 54#define LIO_CN2360_10G_SUBDEVICE 0x05 55#define LIO_CN2350_25G_SUBDEVICE 0x07 56#define LIO_CN2360_25G_SUBDEVICE 0x06 57 58 59/* Endian-swap modes supported by Octeon. */ 60enum lio_pci_swap_mode { 61 LIO_PCI_PASSTHROUGH = 0, 62 LIO_PCI_SWAP_64BIT = 1, 63 LIO_PCI_SWAP_32BIT = 2, 64 LIO_PCI_LW_SWAP_32BIT = 3 65}; 66 67enum { 68 LIO_CFG_TYPE_DEFAULT = 0, 69 LIO_NUM_CFGS, 70}; 71 72#define OCTEON_OUTPUT_INTR (2) 73#define OCTEON_ALL_INTR 0xff 74 75/*--------------- PCI BAR1 index registers -------------*/ 76 77/* BAR1 Mask */ 78#define LIO_PCI_BAR1_ENABLE_CA 1 79#define LIO_PCI_BAR1_ENDIAN_MODE LIO_PCI_SWAP_64BIT 80#define LIO_PCI_BAR1_ENTRY_VALID 1 81#define LIO_PCI_BAR1_MASK ((LIO_PCI_BAR1_ENABLE_CA << 3) | \ 82 (LIO_PCI_BAR1_ENDIAN_MODE << 1) | \ 83 LIO_PCI_BAR1_ENTRY_VALID) 84 85/* 86 * Octeon Device state. 87 * Each octeon device goes through each of these states 88 * as it is initialized. 89 */ 90#define LIO_DEV_BEGIN_STATE 0x0 91#define LIO_DEV_PCI_ENABLE_DONE 0x1 92#define LIO_DEV_PCI_MAP_DONE 0x2 93#define LIO_DEV_DISPATCH_INIT_DONE 0x3 94#define LIO_DEV_INSTR_QUEUE_INIT_DONE 0x4 95#define LIO_DEV_SC_BUFF_POOL_INIT_DONE 0x5 96#define LIO_DEV_MSIX_ALLOC_VECTOR_DONE 0x6 97#define LIO_DEV_RESP_LIST_INIT_DONE 0x7 98#define LIO_DEV_DROQ_INIT_DONE 0x8 99#define LIO_DEV_INTR_SET_DONE 0xa 100#define LIO_DEV_IO_QUEUES_DONE 0xb 101#define LIO_DEV_CONSOLE_INIT_DONE 0xc 102#define LIO_DEV_HOST_OK 0xd 103#define LIO_DEV_CORE_OK 0xe 104#define LIO_DEV_RUNNING 0xf 105#define LIO_DEV_IN_RESET 0x10 106#define LIO_DEV_STATE_INVALID 0x11 107 108#define LIO_DEV_STATES LIO_DEV_STATE_INVALID 109 110/* 111 * Octeon Device interrupts 112 * These interrupt bits are set in int_status filed of 113 * octeon_device structure 114 */ 115#define LIO_DEV_INTR_DMA0_FORCE 0x01 116#define LIO_DEV_INTR_DMA1_FORCE 0x02 117#define LIO_DEV_INTR_PKT_DATA 0x04 118 119#define LIO_RESET_MSECS (3000) 120 121/*---------------------------DISPATCH LIST-------------------------------*/ 122 123/* 124 * The dispatch list entry. 125 * The driver keeps a record of functions registered for each 126 * response header opcode in this structure. Since the opcode is 127 * hashed to index into the driver's list, more than one opcode 128 * can hash to the same entry, in which case the list field points 129 * to a linked list with the other entries. 130 */ 131struct lio_dispatch { 132 /* Singly-linked tail queue node for this entry */ 133 struct lio_stailq_node node; 134 135 /* Singly-linked tail queue head for this entry */ 136 struct lio_stailq_head head; 137 138 /* The opcode for which the dispatch function & arg should be used */ 139 uint16_t opcode; 140 141 /* The function to be called for a packet received by the driver */ 142 lio_dispatch_fn_t dispatch_fn; 143 144 /* 145 * The application specified argument to be passed to the above 146 * function along with the received packet 147 */ 148 void *arg; 149}; 150 151/* The dispatch list structure. */ 152struct lio_dispatch_list { 153 /* access to dispatch list must be atomic */ 154 struct mtx lock; 155 156 /* Count of dispatch functions currently registered */ 157 uint32_t count; 158 159 /* The list of dispatch functions */ 160 struct lio_dispatch *dlist; 161}; 162 163/*----------------------- THE OCTEON DEVICE ---------------------------*/ 164 165#define LIO_MEM_REGIONS 3 166/* 167 * PCI address space information. 168 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 169 * Octeon gets mapped to different physical address spaces in 170 * the kernel. 171 */ 172struct lio_mem_bus_space { 173 struct resource *pci_mem; 174 bus_space_tag_t tag; 175 bus_space_handle_t handle; 176}; 177 178#define LIO_MAX_MAPS 32 179 180struct lio_io_enable { 181 uint64_t iq; 182 uint64_t oq; 183 uint64_t iq64B; 184}; 185 186struct lio_reg_list { 187 uint32_t pci_win_wr_addr; 188 189 uint32_t pci_win_rd_addr_hi; 190 uint32_t pci_win_rd_addr_lo; 191 uint32_t pci_win_rd_addr; 192 193 uint32_t pci_win_wr_data_hi; 194 uint32_t pci_win_wr_data_lo; 195 uint32_t pci_win_wr_data; 196 197 uint32_t pci_win_rd_data; 198}; 199 200#define LIO_MAX_CONSOLE_READ_BYTES 512 201 202typedef int (*octeon_console_print_fn)(struct octeon_device *oct, 203 uint32_t num, char *pre, char *suf); 204struct lio_console { 205 uint32_t active; 206 uint32_t waiting; 207 uint64_t addr; 208 uint32_t buffer_size; 209 uint64_t input_base_addr; 210 uint64_t output_base_addr; 211 octeon_console_print_fn print; 212 char leftover[LIO_MAX_CONSOLE_READ_BYTES]; 213}; 214 215struct lio_board_info { 216 char name[LIO_BOARD_NAME]; 217 char serial_number[LIO_SERIAL_NUM_LEN]; 218 uint64_t major; 219 uint64_t minor; 220}; 221 222struct lio_fn_list { 223 void (*setup_iq_regs) (struct octeon_device *, uint32_t); 224 void (*setup_oq_regs) (struct octeon_device *, uint32_t); 225 226 void (*process_interrupt_regs) (void *); 227 uint64_t (*msix_interrupt_handler) (void *); 228 int (*soft_reset) (struct octeon_device *); 229 int (*setup_device_regs) (struct octeon_device *); 230 void (*bar1_idx_setup) (struct octeon_device *, uint64_t, 231 uint32_t, int); 232 void (*bar1_idx_write) (struct octeon_device *, uint32_t, 233 uint32_t); 234 uint32_t (*bar1_idx_read) (struct octeon_device *, uint32_t); 235 uint32_t (*update_iq_read_idx) (struct lio_instr_queue *); 236 237 void (*enable_interrupt) (struct octeon_device *, uint8_t); 238 void (*disable_interrupt) (struct octeon_device *, uint8_t); 239 240 int (*enable_io_queues) (struct octeon_device *); 241 void (*disable_io_queues) (struct octeon_device *); 242}; 243 244/* Must be multiple of 8, changing breaks ABI */ 245#define LIO_BOOTMEM_NAME_LEN 128 246 247/* 248 * Structure for named memory blocks 249 * Number of descriptors 250 * available can be changed without affecting compatibility, 251 * but name length changes require a bump in the bootmem 252 * descriptor version 253 * Note: This structure must be naturally 64 bit aligned, as a single 254 * memory image will be used by both 32 and 64 bit programs. 255 */ 256struct cvmx_bootmem_named_block_desc { 257 /* Base address of named block */ 258 uint64_t base_addr; 259 260 /* Size actually allocated for named block */ 261 uint64_t size; 262 263 /* name of named block */ 264 char name[LIO_BOOTMEM_NAME_LEN]; 265}; 266 267struct lio_fw_info { 268 uint32_t max_nic_ports; /* max nic ports for the device */ 269 uint32_t num_gmx_ports; /* num gmx ports */ 270 uint64_t app_cap_flags; /* firmware cap flags */ 271 272 /* 273 * The core application is running in this mode. 274 * See octeon-drv-opcodes.h for values. 275 */ 276 uint32_t app_mode; 277 char lio_firmware_version[32]; 278}; 279 280struct lio_callout { 281 struct callout timer; 282 void *ctxptr; 283 uint64_t ctxul; 284}; 285 286#define LIO_NIC_STARTER_TIMEOUT 30000 /* 30000ms (30s) */ 287 288struct lio_tq { 289 struct taskqueue *tq; 290 struct timeout_task work; 291 void *ctxptr; 292 uint64_t ctxul; 293}; 294 295struct lio_if_props { 296 /* 297 * Each interface in the Octeon device has a network 298 * device pointer (used for OS specific calls). 299 */ 300 int rx_on; 301 int gmxport; 302 struct ifnet *ifp; 303}; 304 305#define LIO_MSIX_PO_INT 0x1 306#define LIO_MSIX_PI_INT 0x2 307 308struct lio_pf_vf_hs_word { 309#if BYTE_ORDER == LITTLE_ENDIAN 310 /* PKIND value assigned for the DPI interface */ 311 uint64_t pkind:8; 312 313 /* OCTEON core clock multiplier */ 314 uint64_t core_tics_per_us:16; 315 316 /* OCTEON coprocessor clock multiplier */ 317 uint64_t coproc_tics_per_us:16; 318 319 /* app that currently running on OCTEON */ 320 uint64_t app_mode:8; 321 322 /* RESERVED */ 323 uint64_t reserved:16; 324 325#else /* BYTE_ORDER != LITTLE_ENDIAN */ 326 327 /* RESERVED */ 328 uint64_t reserved:16; 329 330 /* app that currently running on OCTEON */ 331 uint64_t app_mode:8; 332 333 /* OCTEON coprocessor clock multiplier */ 334 uint64_t coproc_tics_per_us:16; 335 336 /* OCTEON core clock multiplier */ 337 uint64_t core_tics_per_us:16; 338 339 /* PKIND value assigned for the DPI interface */ 340 uint64_t pkind:8; 341#endif /* BYTE_ORDER == LITTLE_ENDIAN */ 342}; 343 344struct lio_sriov_info { 345 346 /* Actual rings left for PF device */ 347 uint32_t num_pf_rings; 348 349 /* SRN of PF usable IO queues */ 350 uint32_t pf_srn; 351 352 /* total pf rings */ 353 uint32_t trs; 354}; 355 356struct lio_ioq_vector { 357 struct octeon_device *oct_dev; 358 struct resource *msix_res; 359 void *tag; 360 int droq_index; 361 int vector; 362 cpuset_t affinity_mask; 363 uint32_t ioq_num; 364}; 365 366/* 367 * The Octeon device. 368 * Each Octeon device has this structure to represent all its 369 * components. 370 */ 371struct octeon_device { 372 /* Lock for PCI window configuration accesses */ 373 struct mtx pci_win_lock; 374 375 /* Lock for memory accesses */ 376 struct mtx mem_access_lock; 377 378 /* PCI device pointer */ 379 device_t device; 380 381 /* Chip specific information. */ 382 void *chip; 383 384 /* Number of interfaces detected in this octeon device. */ 385 uint32_t ifcount; 386 387 struct lio_if_props props; 388 389 /* Octeon Chip type. */ 390 uint16_t chip_id; 391 392 uint16_t rev_id; 393 394 uint16_t subdevice_id; 395 396 uint16_t pf_num; 397 398 399 /* This device's id - set by the driver. */ 400 uint32_t octeon_id; 401 402 /* This device's PCIe port used for traffic. */ 403 uint16_t pcie_port; 404 405 uint16_t flags; 406#define LIO_FLAG_MSIX_ENABLED (uint32_t)(1 << 2) 407 408 /* The state of this device */ 409 volatile int status; 410 411 /* memory mapped io range */ 412 struct lio_mem_bus_space mem_bus_space[LIO_MEM_REGIONS]; 413 414 struct lio_reg_list reg_list; 415 416 struct lio_fn_list fn_list; 417 418 struct lio_board_info boardinfo; 419 420 uint32_t num_iqs; 421 422 /* The pool containing pre allocated buffers used for soft commands */ 423 struct lio_sc_buffer_pool sc_buf_pool; 424 425 /* The input instruction queues */ 426 struct lio_instr_queue *instr_queue[LIO_MAX_POSSIBLE_INSTR_QUEUES]; 427 428 /* The doubly-linked list of instruction response */ 429 struct lio_response_list response_list[LIO_MAX_RESPONSE_LISTS]; 430 431 uint32_t num_oqs; 432 433 /* The DROQ output queues */ 434 struct lio_droq *droq[LIO_MAX_POSSIBLE_OUTPUT_QUEUES]; 435 436 struct lio_io_enable io_qmask; 437 438 /* List of dispatch functions */ 439 struct lio_dispatch_list dispatch; 440 441 uint32_t int_status; 442 443 /* Physical location of the cvmx_bootmem_desc_t in octeon memory */ 444 uint64_t bootmem_desc_addr; 445 446 /* 447 * Placeholder memory for named blocks. 448 * Assumes single-threaded access 449 */ 450 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; 451 452 /* Address of consoles descriptor */ 453 uint64_t console_desc_addr; 454 455 /* Number of consoles available. 0 means they are inaccessible */ 456 uint32_t num_consoles; 457 458 /* Console caches */ 459 struct lio_console console[LIO_MAX_MAPS]; 460 461 /* Console named block info */ 462 struct { 463 uint64_t dram_region_base; 464 int bar1_index; 465 } console_nb_info; 466 467 /* Coprocessor clock rate. */ 468 uint64_t coproc_clock_rate; 469 470 /* 471 * The core application is running in this mode. See lio_common.h 472 * for values. 473 */ 474 uint32_t app_mode; 475 476 struct lio_fw_info fw_info; 477 478 /* The name given to this device. */ 479 char device_name[32]; 480 481 struct lio_tq dma_comp_tq; 482 483 /* Lock for dma response list */ 484 struct mtx cmd_resp_wqlock; 485 uint32_t cmd_resp_state; 486 487 struct lio_tq check_db_tq[LIO_MAX_POSSIBLE_INSTR_QUEUES]; 488 489 struct lio_callout console_timer[LIO_MAX_MAPS]; 490 491 int num_msix_irqs; 492 493 /* For PF, there is one non-ioq interrupt handler */ 494 struct resource *msix_res; 495 int aux_vector; 496 void *tag; 497 498#define INTRNAMSIZ (32) 499#define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 500 501 struct lio_sriov_info sriov_info; 502 503 struct lio_pf_vf_hs_word pfvf_hsword; 504 505 int msix_on; 506 507 /* IOq information of it's corresponding MSI-X interrupt. */ 508 struct lio_ioq_vector *ioq_vector; 509 510 int rx_pause; 511 int tx_pause; 512 513 /* TX/RX process pkt budget */ 514 uint32_t rx_budget; 515 uint32_t tx_budget; 516 517 struct octeon_link_stats link_stats; /* stastics from firmware */ 518 519 struct proc *watchdog_task; 520 521 volatile bool cores_crashed; 522 523 uint32_t rx_coalesce_usecs; 524 uint32_t rx_max_coalesced_frames; 525 uint32_t tx_max_coalesced_frames; 526 527#define OCTEON_UBOOT_BUFFER_SIZE 512 528 char uboot_version[OCTEON_UBOOT_BUFFER_SIZE]; 529 int uboot_len; 530 int uboot_sidx, uboot_eidx; 531 532 struct { 533 int bus; 534 int dev; 535 int func; 536 } loc; 537 538 volatile int *adapter_refcount; /* reference count of adapter */ 539}; 540 541#define LIO_DRV_ONLINE 1 542#define LIO_DRV_OFFLINE 2 543#define LIO_CN23XX_PF(oct) ((oct)->chip_id == LIO_CN23XX_PF_VID) 544#define LIO_CHIP_CONF(oct, TYPE) \ 545 (((struct lio_ ## TYPE *)((oct)->chip))->conf) 546#define MAX_IO_PENDING_PKT_COUNT 100 547 548/*------------------ Function Prototypes ----------------------*/ 549 550/* Initialize device list memory */ 551void lio_init_device_list(int conf_type); 552 553/* Free memory for Input and Output queue structures for a octeon device */ 554void lio_free_device_mem(struct octeon_device *oct); 555 556/* 557 * Look up a free entry in the octeon_device table and allocate resources 558 * for the octeon_device structure for an octeon device. Called at init 559 * time. 560 */ 561struct octeon_device *lio_allocate_device(device_t device); 562 563/* 564 * Register a device's bus location at initialization time. 565 * @param oct - pointer to the octeon device structure. 566 * @param bus - PCIe bus # 567 * @param dev - PCIe device # 568 * @param func - PCIe function # 569 * @param is_pf - TRUE for PF, FALSE for VF 570 * @return reference count of device's adapter 571 */ 572int lio_register_device(struct octeon_device *oct, int bus, int dev, 573 int func, int is_pf); 574 575/* 576 * Deregister a device at de-initialization time. 577 * @param oct - pointer to the octeon device structure. 578 * @return reference count of device's adapter 579 */ 580int lio_deregister_device(struct octeon_device *oct); 581 582/* 583 * Initialize the driver's dispatch list which is a mix of a hash table 584 * and a linked list. This is done at driver load time. 585 * @param octeon_dev - pointer to the octeon device structure. 586 * @return 0 on success, else -ve error value 587 */ 588int lio_init_dispatch_list(struct octeon_device *octeon_dev); 589 590/* 591 * Delete the driver's dispatch list and all registered entries. 592 * This is done at driver unload time. 593 * @param octeon_dev - pointer to the octeon device structure. 594 */ 595void lio_delete_dispatch_list(struct octeon_device *octeon_dev); 596 597/* 598 * Initialize the core device fields with the info returned by the FW. 599 * @param recv_info - Receive info structure 600 * @param buf - Receive buffer 601 */ 602int lio_core_drv_init(struct lio_recv_info *recv_info, void *buf); 603 604/* 605 * Gets the dispatch function registered to receive packets with a 606 * given opcode/subcode. 607 * @param octeon_dev - the octeon device pointer. 608 * @param opcode - the opcode for which the dispatch function 609 * is to checked. 610 * @param subcode - the subcode for which the dispatch function 611 * is to checked. 612 * 613 * @return Success: lio_dispatch_fn_t (dispatch function pointer) 614 * @return Failure: NULL 615 * 616 * Looks up the dispatch list to get the dispatch function for a 617 * given opcode. 618 */ 619lio_dispatch_fn_t lio_get_dispatch(struct octeon_device *octeon_dev, 620 uint16_t opcode, uint16_t subcode); 621 622/* 623 * Get the octeon device pointer. 624 * @param octeon_id - The id for which the octeon device pointer is required. 625 * @return Success: Octeon device pointer. 626 * @return Failure: NULL. 627 */ 628struct octeon_device *lio_get_device(uint32_t octeon_id); 629 630/* 631 * Get the octeon id assigned to the octeon device passed as argument. 632 * This function is exported to other modules. 633 * @param dev - octeon device pointer passed as a void *. 634 * @return octeon device id 635 */ 636int lio_get_device_id(void *dev); 637 638static inline uint16_t 639OCTEON_MAJOR_REV(struct octeon_device *oct) 640{ 641 642 uint16_t rev = (oct->rev_id & 0xC) >> 2; 643 644 return ((rev == 0) ? 1 : rev); 645} 646 647static inline uint16_t 648OCTEON_MINOR_REV(struct octeon_device *oct) 649{ 650 651 return (oct->rev_id & 0x3); 652} 653 654/* 655 * Read windowed register. 656 * @param oct - pointer to the Octeon device. 657 * @param addr - Address of the register to read. 658 * 659 * This routine is called to read from the indirectly accessed 660 * Octeon registers that are visible through a PCI BAR0 mapped window 661 * register. 662 * @return - 64 bit value read from the register. 663 */ 664 665uint64_t lio_pci_readq(struct octeon_device *oct, uint64_t addr); 666 667/* 668 * Write windowed register. 669 * @param oct - pointer to the Octeon device. 670 * @param val - Value to write 671 * @param addr - Address of the register to write 672 * 673 * This routine is called to write to the indirectly accessed 674 * Octeon registers that are visible through a PCI BAR0 mapped window 675 * register. 676 * @return Nothing. 677 */ 678void lio_pci_writeq(struct octeon_device *oct, uint64_t val, uint64_t addr); 679 680/* 681 * Checks if memory access is okay 682 * 683 * @param oct which octeon to send to 684 * @return Zero on success, negative on failure. 685 */ 686int lio_mem_access_ok(struct octeon_device *oct); 687 688/* 689 * Waits for DDR initialization. 690 * 691 * @param oct which octeon to send to 692 * @param timeout_in_ms pointer to how long to wait until DDR is initialized 693 * in ms. 694 * If contents are 0, it waits until contents are non-zero 695 * before starting to check. 696 * @return Zero on success, negative on failure. 697 */ 698int lio_wait_for_ddr_init(struct octeon_device *oct, 699 unsigned long *timeout_in_ms); 700 701/* 702 * Wait for u-boot to boot and be waiting for a command. 703 * 704 * @param wait_time_hundredths 705 * Maximum time to wait 706 * 707 * @return Zero on success, negative on failure. 708 */ 709int lio_wait_for_bootloader(struct octeon_device *oct, 710 uint32_t wait_time_hundredths); 711 712/* 713 * Initialize console access 714 * 715 * @param oct which octeon initialize 716 * @return Zero on success, negative on failure. 717 */ 718int lio_init_consoles(struct octeon_device *oct); 719 720/* 721 * Adds access to a console to the device. 722 * 723 * @param oct: which octeon to add to 724 * @param console_num: which console 725 * @param dbg_enb: ptr to debug enablement string, one of: 726 * * NULL for no debug output (i.e. disabled) 727 * * empty string enables debug output (via default method) 728 * * specific string to enable debug console output 729 * 730 * @return Zero on success, negative on failure. 731 */ 732int lio_add_console(struct octeon_device *oct, uint32_t console_num, 733 char *dbg_enb); 734 735/* write or read from a console */ 736int lio_console_write(struct octeon_device *oct, uint32_t console_num, 737 char *buffer, uint32_t write_request_size, 738 uint32_t flags); 739 740/* Removes all attached consoles. */ 741void lio_remove_consoles(struct octeon_device *oct); 742 743/* 744 * Send a string to u-boot on console 0 as a command. 745 * 746 * @param oct which octeon to send to 747 * @param cmd_str String to send 748 * @param wait_hundredths Time to wait for u-boot to accept the command. 749 * 750 * @return Zero on success, negative on failure. 751 */ 752int lio_console_send_cmd(struct octeon_device *oct, char *cmd_str, 753 uint32_t wait_hundredths); 754 755/* 756 * Parses, validates, and downloads firmware, then boots associated cores. 757 * @param oct which octeon to download firmware to 758 * @param data - The complete firmware file image 759 * @param size - The size of the data 760 * 761 * @return 0 if success. 762 * -EINVAL if file is incompatible or badly formatted. 763 * -ENODEV if no handler was found for the application type or an 764 * invalid octeon id was passed. 765 */ 766int lio_download_firmware(struct octeon_device *oct, const uint8_t *data, 767 size_t size); 768 769char *lio_get_state_string(volatile int *state_ptr); 770 771/* 772 * Sets up instruction queues for the device 773 * @param oct which octeon to setup 774 * 775 * @return 0 if success. 1 if fails 776 */ 777int lio_setup_instr_queue0(struct octeon_device *oct); 778 779/* 780 * Sets up output queues for the device 781 * @param oct which octeon to setup 782 * 783 * @return 0 if success. 1 if fails 784 */ 785int lio_setup_output_queue0(struct octeon_device *oct); 786 787int lio_get_tx_qsize(struct octeon_device *oct, uint32_t q_no); 788 789int lio_get_rx_qsize(struct octeon_device *oct, uint32_t q_no); 790 791/* 792 * Retrieve the config for the device 793 * @param oct which octeon 794 * @param card_type type of card 795 * 796 * @returns pointer to configuration 797 */ 798void *lio_get_config_info(struct octeon_device *oct, uint16_t card_type); 799 800/* 801 * Gets the octeon device configuration 802 * @return - pointer to the octeon configuration struture 803 */ 804struct lio_config *lio_get_conf(struct octeon_device *oct); 805 806void lio_free_ioq_vector(struct octeon_device *oct); 807int lio_allocate_ioq_vector(struct octeon_device *oct); 808void lio_enable_irq(struct lio_droq *droq, struct lio_instr_queue *iq); 809 810static inline uint32_t 811lio_read_pci_cfg(struct octeon_device *oct, uint32_t reg) 812{ 813 814 return (pci_read_config(oct->device, reg, 4)); 815} 816 817static inline void 818lio_write_pci_cfg(struct octeon_device *oct, uint32_t reg, uint32_t value) 819{ 820 821 pci_write_config(oct->device, reg, value, 4); 822} 823 824static inline uint8_t 825lio_read_csr8(struct octeon_device *oct, uint32_t reg) 826{ 827 828 return (bus_space_read_1(oct->mem_bus_space[0].tag, 829 oct->mem_bus_space[0].handle, reg)); 830} 831 832static inline void 833lio_write_csr8(struct octeon_device *oct, uint32_t reg, uint8_t val) 834{ 835 836 bus_space_write_1(oct->mem_bus_space[0].tag, 837 oct->mem_bus_space[0].handle, reg, val); 838} 839 840static inline uint16_t 841lio_read_csr16(struct octeon_device *oct, uint32_t reg) 842{ 843 844 return (bus_space_read_2(oct->mem_bus_space[0].tag, 845 oct->mem_bus_space[0].handle, reg)); 846} 847 848static inline void 849lio_write_csr16(struct octeon_device *oct, uint32_t reg, uint16_t val) 850{ 851 852 bus_space_write_2(oct->mem_bus_space[0].tag, 853 oct->mem_bus_space[0].handle, reg, val); 854} 855 856static inline uint32_t 857lio_read_csr32(struct octeon_device *oct, uint32_t reg) 858{ 859 860 return (bus_space_read_4(oct->mem_bus_space[0].tag, 861 oct->mem_bus_space[0].handle, reg)); 862} 863 864static inline void 865lio_write_csr32(struct octeon_device *oct, uint32_t reg, uint32_t val) 866{ 867 868 bus_space_write_4(oct->mem_bus_space[0].tag, 869 oct->mem_bus_space[0].handle, reg, val); 870} 871 872static inline uint64_t 873lio_read_csr64(struct octeon_device *oct, uint32_t reg) 874{ 875 876#ifdef __i386__ 877 return (lio_read_csr32(oct, reg) | 878 ((uint64_t)lio_read_csr32(oct, reg + 4) << 32)); 879#else 880 return (bus_space_read_8(oct->mem_bus_space[0].tag, 881 oct->mem_bus_space[0].handle, reg)); 882#endif 883} 884 885static inline void 886lio_write_csr64(struct octeon_device *oct, uint32_t reg, uint64_t val) 887{ 888 889#ifdef __i386__ 890 lio_write_csr32(oct, reg, (uint32_t)val); 891 lio_write_csr32(oct, reg + 4, val >> 32); 892#else 893 bus_space_write_8(oct->mem_bus_space[0].tag, 894 oct->mem_bus_space[0].handle, reg, val); 895#endif 896} 897 898#endif /* _LIO_DEVICE_H_ */ 899