Searched refs:clk (Results 276 - 300 of 4090) sorted by relevance

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/linux-master/sound/soc/mediatek/mt8186/
H A Dmt8186-audsys-clk.c3 // mt8186-audsys-clk.h -- Mediatek 8186 audsys clock control
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
12 #include "mt8186-audsys-clk.h"
91 struct clk *clk; local
103 clk = cl->clk;
104 clk_unregister_gate(clk);
113 struct clk *cl local
[all...]
/linux-master/drivers/fpga/
H A Dxilinx-pr-decoupler.c10 #include <linux/clk.h>
30 struct clk *clk; member in struct:xlnx_pr_decoupler_data
50 err = clk_enable(priv->clk);
59 clk_disable(priv->clk);
70 err = clk_enable(priv->clk);
76 clk_disable(priv->clk);
121 priv->clk = devm_clk_get(&pdev->dev, "aclk");
122 if (IS_ERR(priv->clk))
123 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
[all...]
/linux-master/drivers/pwm/
H A Dpwm-ep93xx.c22 #include <linux/clk.h>
38 struct clk *clk; member in struct:ep93xx_pwm
75 clk_disable_unprepare(ep93xx_pwm->clk);
83 ret = clk_prepare_enable(ep93xx_pwm->clk);
92 clk_disable_unprepare(ep93xx_pwm->clk);
98 clk_disable_unprepare(ep93xx_pwm->clk);
109 ret = clk_prepare_enable(ep93xx_pwm->clk);
114 c = clk_get_rate(ep93xx_pwm->clk);
141 clk_disable_unprepare(ep93xx_pwm->clk);
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/linux-master/drivers/clk/meson/
H A Dvid-pll-div.c7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
14 meson_vid_pll_div_data(struct clk_regmap *clk) argument
16 return (struct meson_vid_pll_div_data *)clk->data;
78 struct clk_regmap *clk = to_clk_regmap(hw); local
79 struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk);
82 div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
83 meson_parm_read(clk->map, &pll_div->sel));
H A Dclk-regmap.h10 #include <linux/clk-provider.h>
51 clk_get_regmap_gate_data(struct clk_regmap *clk) argument
53 return (struct clk_regmap_gate_data *)clk->data;
79 clk_get_regmap_div_data(struct clk_regmap *clk) argument
81 return (struct clk_regmap_div_data *)clk->data;
109 clk_get_regmap_mux_data(struct clk_regmap *clk) argument
111 return (struct clk_regmap_mux_data *)clk->data;
/linux-master/drivers/clk/mxs/
H A Dclk-pll.c6 #include <linux/clk-provider.h>
11 #include "clk.h"
82 struct clk *mxs_clk_pll(const char *name, const char *parent_name,
86 struct clk *clk; local
104 clk = clk_register(NULL, &pll->hw);
105 if (IS_ERR(clk))
108 return clk;
/linux-master/drivers/clk/sunxi/
H A Dclk-sun4i-pll3.c8 #include <linux/clk-provider.h>
28 struct clk *clk; local
57 clk = clk_register_composite(NULL, clk_name,
63 if (IS_ERR(clk)) {
68 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
78 clk_unregister_composite(clk);
89 CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
/linux-master/arch/loongarch/kernel/
H A Denv.c8 #include <linux/clk.h>
63 struct clk *clk; local
70 clk = of_clk_get(np, 0);
71 if (IS_ERR(clk))
74 cpu_clock_freq = clk_get_rate(clk);
75 clk_put(clk);
/linux-master/sound/soc/mediatek/mt8195/
H A Dmt8195-afe-clk.c3 * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
10 #include <linux/clk.h>
13 #include "mt8195-afe-clk.h"
15 #include "mt8195-audsys-clk.h"
247 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
248 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
251 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
252 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
268 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
269 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APL
413 mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) argument
431 mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk) argument
440 mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk) argument
457 mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk) argument
465 mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) argument
482 mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) argument
490 mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, unsigned int rate) argument
507 mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, struct clk *parent) argument
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/linux-master/drivers/clocksource/
H A Dtimer-lpc32xx.c14 #include <linux/clk.h>
159 struct clk *clk; local
162 clk = of_clk_get_by_name(np, "timerclk");
163 if (IS_ERR(clk)) {
164 pr_err("clock get failed (%ld)\n", PTR_ERR(clk));
165 return PTR_ERR(clk);
168 ret = clk_prepare_enable(clk);
192 rate = clk_get_rate(clk);
210 clk_disable_unprepare(clk);
220 struct clk *clk; local
[all...]
H A Dtimer-milbeaut.c6 #include <linux/clk.h>
51 struct clock_event_device *clk = dev_id; local
52 struct timer_of *to = to_timer_of(clk);
59 clk->event_handler(clk);
87 static int mlb_set_state_periodic(struct clock_event_device *clk) argument
89 struct timer_of *to = to_timer_of(clk);
97 static int mlb_set_state_oneshot(struct clock_event_device *clk) argument
99 struct timer_of *to = to_timer_of(clk);
106 static int mlb_set_state_shutdown(struct clock_event_device *clk) argument
114 mlb_clkevt_next_event(unsigned long event, struct clock_event_device *clk) argument
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/linux-master/drivers/clk/ti/
H A Dclk-3xxx.c11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/clk/ti.h>
37 * @clk: struct clk * being enabled
46 static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, argument
51 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
67 * @clk: struct clk * being enabled
80 omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, argument
117 omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, struct clk_omap_reg *idlest_reg, u8 *idlest_bit, u8 *idlest_val) argument
147 am35xx_clk_find_idlest(struct clk_hw_omap *clk, struct clk_omap_reg *idlest_reg, u8 *idlest_bit, u8 *idlest_val) argument
171 am35xx_clk_find_companion(struct clk_hw_omap *clk, struct clk_omap_reg *other_reg, u8 *other_bit) argument
198 am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, struct clk_omap_reg *idlest_reg, u8 *idlest_bit, u8 *idlest_val) argument
[all...]
H A Dclk.c11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/clk/ti.h>
118 * Eventually we could standardize to using '_' for clk-*.c files to follow the
175 struct clk *clk; local
216 child = of_get_child_by_name(parent, "clk");
234 clk = of_clk_get_from_provider(&clkspec);
236 if (!IS_ERR(clk)) {
237 c->lk.clk
519 struct clk *clk; local
587 ti_clk_add_alias(struct clk *clk, const char *con) argument
622 struct clk *clk; local
653 struct clk *clk; local
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/linux-master/drivers/clk/
H A Dclk.c6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
100 #include <trace/events/clk.h>
102 struct clk { struct
131 * clk_pm_runtime_get_all() - Runtime "get" all clk provider devices
133 * Call clk_pm_runtime_get() on all runtime PM enabled clks in the clk tre
356 __clk_get_name(const struct clk *clk) argument
368 __clk_get_hw(struct clk *clk) argument
564 __clk_get_enable_count(struct clk *clk) argument
623 __clk_is_enabled(struct clk *clk) argument
953 clk_rate_exclusive_put(struct clk *clk) argument
1019 clk_rate_exclusive_get(struct clk *clk) argument
1035 struct clk *clk = data; local
1040 devm_clk_rate_exclusive_get(struct device *dev, struct clk *clk) argument
1103 clk_unprepare(struct clk *clk) argument
1184 clk_prepare(struct clk *clk) argument
1241 clk_disable(struct clk *clk) argument
1356 struct clk_core *clk; local
1406 clk_enable(struct clk *clk) argument
1430 clk_is_enabled_when_prepared(struct clk *clk) argument
1799 clk_round_rate(struct clk *clk, unsigned long rate) argument
1915 clk_get_accuracy(struct clk *clk) argument
2001 clk_get_rate(struct clk *clk) argument
2596 clk_set_rate(struct clk *clk, unsigned long rate) argument
2639 clk_set_rate_exclusive(struct clk *clk, unsigned long rate) argument
2667 clk_set_rate_range_nolock(struct clk *clk, unsigned long min, unsigned long max) argument
2746 clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) argument
2770 clk_set_min_rate(struct clk *clk, unsigned long rate) argument
2788 clk_set_max_rate(struct clk *clk, unsigned long rate) argument
2805 clk_get_parent(struct clk *clk) argument
2857 clk_has_parent(const struct clk *clk, const struct clk *parent) argument
2955 clk_set_parent(struct clk *clk, struct clk *parent) argument
3024 clk_set_phase(struct clk *clk, int degrees) argument
3075 clk_get_phase(struct clk *clk) argument
3191 clk_set_duty_cycle(struct clk *clk, unsigned int num, unsigned int den) argument
3247 clk_get_scaled_duty_cycle(struct clk *clk, unsigned int scale) argument
4103 clk_core_link_consumer(struct clk_core *core, struct clk *clk) argument
4114 clk_core_unlink_consumer(struct clk *clk) argument
4131 struct clk *clk; local
4152 free_clk(struct clk *clk) argument
4173 struct clk *clk; local
4558 clk_unregister(struct clk *clk) argument
4648 struct clk *clk; local
4715 struct clk *clk; local
4744 __clk_put(struct clk *clk) argument
4801 clk_notifier_register(struct clk *clk, struct notifier_block *nb) argument
4849 clk_notifier_unregister(struct clk *clk, struct notifier_block *nb) argument
4882 struct clk *clk; member in struct:clk_notifier_devres
4893 devm_clk_notifier_register(struct device *dev, struct clk *clk, struct notifier_block *nb) argument
5247 struct clk *clk; local
5373 struct clk *clk; local
5461 struct clk *clk = of_clk_get(np, i); local
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H A Dclk-nspire.c7 #include <linux/clk-provider.h>
41 static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk) argument
44 clk->base_clock = 48 * MHZ;
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
48 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN);
49 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
52 static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk) argument
55 clk->base_clock = 27 * MHZ;
57 clk
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/linux-master/drivers/clk/tegra/
H A Dclk-tegra20.c7 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
17 #include "clk.h"
18 #include "clk-id.h"
157 static struct clk **clks;
502 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
503 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
504 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
505 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
627 struct clk *cl local
706 struct clk *clk; local
726 struct clk *clk; local
786 struct clk *clk; local
857 struct clk *clk; local
1077 struct clk *clk; local
1172 struct clk *clk; local
[all...]
H A Dclk.c7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
21 #include "clk.h"
31 static struct clk **clks;
223 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
238 clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);
258 struct clk *clks[], int clk_max)
260 struct clk *clk; local
272 struct clk *clk; local
[all...]
/linux-master/drivers/phy/allwinner/
H A Dphy-sun9i-usb.c14 #include <linux/clk.h>
39 struct clk *clk; member in struct:sun9i_usb_phy
40 struct clk *hsic_clk;
71 ret = clk_prepare_enable(phy->clk);
90 clk_disable_unprepare(phy->clk);
103 clk_disable_unprepare(phy->clk);
127 phy->clk = devm_clk_get(dev, "hsic_480M");
128 if (IS_ERR(phy->clk)) {
130 return PTR_ERR(phy->clk);
[all...]
/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c8 #include <linux/clk-provider.h>
415 /* Power down PLL, disable clk output and dividers */
530 static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk, argument
534 const char *name = clk_src_names[clk->clk_id];
537 clk->div.reg = reg;
538 clk->mux.reg = reg;
539 clk->gate.reg = reg;
541 lpc18xx_fill_parent_names(parents, clk->mux.table, clk
550 lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk, void __iomem *reg_base, int n) argument
578 lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk *clk, void __iomem *base) argument
600 struct clk *clk; local
[all...]
/linux-master/drivers/phy/renesas/
H A Dphy-rcar-gen3-usb3.c8 #include <linux/clk.h>
137 struct clk *clk; local
152 clk = devm_clk_get(dev, "usb3s_clk");
153 if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
154 r->usb3s_clk = !!clk_get_rate(clk);
155 clk_disable_unprepare(clk);
157 clk = devm_clk_get(dev, "usb_extal");
158 if (!IS_ERR(clk)
[all...]
/linux-master/drivers/mmc/host/
H A Dsdhci-spear.c16 #include <linux/clk.h>
32 struct clk *clk; member in struct:spear_sdhci
76 /* clk enable */
77 sdhci->clk = devm_clk_get(&pdev->dev, NULL);
78 if (IS_ERR(sdhci->clk)) {
79 ret = PTR_ERR(sdhci->clk);
84 ret = clk_prepare_enable(sdhci->clk);
90 ret = clk_set_rate(sdhci->clk, 50000000);
92 dev_dbg(&pdev->dev, "Error setting desired clk, cl
[all...]
/linux-master/drivers/interconnect/
H A Dicc-clk.c6 #include <linux/clk.h>
8 #include <linux/interconnect-clk.h>
12 struct clk *clk; member in struct:icc_clk_node
30 if (!qn || !qn->clk)
35 clk_disable_unprepare(qn->clk);
42 ret = clk_prepare_enable(qn->clk);
48 return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw));
55 if (!qn || !qn->clk)
58 *peak = Bps_to_icc(clk_get_rate(qn->clk));
[all...]
/linux-master/drivers/gpu/host1x/
H A Dmipi.c23 #include <linux/clk.h>
91 unsigned long clk; member in struct:tegra_mipi_pad
124 struct clk *clk; member in struct:tegra_mipi
153 err = clk_enable(mipi->clk);
169 clk_disable(mipi->clk);
179 err = clk_enable(mipi->clk);
308 clk_disable(device->mipi->clk);
321 err = clk_enable(device->mipi->clk);
339 u32 clk local
[all...]
/linux-master/drivers/hwmon/
H A Dsparx5-temp.c8 #include <linux/clk.h>
26 struct clk *clk; member in struct:s5_hwmon
32 u32 clk = clk_get_rate(hwmon->clk) / USEC_PER_SEC; local
35 val |= FIELD_PREP(TEMP_CFG_CYCLES, clk);
118 hwmon->clk = devm_clk_get_enabled(&pdev->dev, NULL);
119 if (IS_ERR(hwmon->clk))
120 return PTR_ERR(hwmon->clk);
/linux-master/drivers/usb/chipidea/
H A Dci_hdrc_usb2.c8 #include <linux/clk.h>
23 struct clk *clk; member in struct:ci_hdrc_usb2_priv
73 priv->clk = devm_clk_get_optional(dev, NULL);
74 if (IS_ERR(priv->clk))
75 return PTR_ERR(priv->clk);
77 ret = clk_prepare_enable(priv->clk);
104 clk_disable_unprepare(priv->clk);
114 clk_disable_unprepare(priv->clk);

Completed in 239 milliseconds

<<11121314151617181920>>