Searched refs:params (Results 276 - 300 of 2217) sorted by path

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/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.c206 const struct dtbclk_dto_params *params)
210 int req_dtbclk_khz = params->pixclk_khz / 4;
212 if (params->ref_dtbclk_khz && req_dtbclk_khz) {
216 modulo = params->ref_dtbclk_khz * 1000;
219 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
220 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
222 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
223 DTBCLK_DTO_ENABLE[params->otg_inst], 1);
225 REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
226 DTBCLKDTO_ENABLE_STATUS[params
204 dccg32_set_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) argument
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H A Ddcn32_mmhubbub.c77 struct mcif_warmup_params *params)
80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5};
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5);
86 // REG_SET(MMHUBBUB_WARMUP_P_VMID, 0, MMHUBBUB_WARMUP_P_VMID, params->p_vmid);
91 MMHUBBUB_WARMUP_INC_ADDR, params->address_increment >> 5);
104 struct mcif_buf_params *params,
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
111 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
115 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params
76 mmhubbub32_warmup_mcif(struct mcif_wb *mcif_wb, struct mcif_warmup_params *params) argument
103 mmhubbub32_config_mcif_buf(struct mcif_wb *mcif_wb, struct mcif_buf_params *params, unsigned int dest_height) argument
156 mmhubbub32_config_mcif_arb(struct mcif_wb *mcif_wb, struct mcif_arb_params *params) argument
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H A Ddcn32_mpc.c170 const struct pwl_params *params)
192 cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
199 const struct pwl_params *params)
221 cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
263 const struct pwl_params *params,
270 if (params == NULL) {
287 mpc32_program_post1dluta_settings(mpc, mpcc_id, params);
289 mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);
292 mpc, mpcc_id, params->rgb_resulted, params
167 mpc32_program_post1dluta_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) argument
196 mpc32_program_post1dlutb_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) argument
261 mpc32_program_post1dlut( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
343 mpc32_program_shaper_luta_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
493 mpc32_program_shaper_lutb_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
708 mpc32_program_shaper( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
904 mpc32_program_3dlut( struct mpc *mpc, const struct tetrahedral_params *params, int mpcc_id) argument
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H A Ddcn32_mpc.h314 const struct tetrahedral_params *params,
318 const struct pwl_params *params,
322 const struct pwl_params *params,
345 const struct pwl_params *params);
349 const struct pwl_params *params);
361 const struct pwl_params *params,
365 const struct pwl_params *params,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dccg.c284 const struct dtbclk_dto_params *params)
288 int req_dtbclk_khz = params->pixclk_khz / 4;
290 if (params->ref_dtbclk_khz && req_dtbclk_khz) {
293 switch (params->otg_inst) {
309 modulo = params->ref_dtbclk_khz * 1000;
312 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
313 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
315 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
316 DTBCLK_DTO_ENABLE[params->otg_inst], 1);
318 REG_WAIT(OTG_PIXEL_RATE_CNTL[params
282 dccg35_set_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp.c204 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
221 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
228 dpp1_cm_program_regamma_luta_settings(dpp_base, params);
230 dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
232 dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
233 params->hw_points_num);
234 dpp->pwl_data = *params;
203 dpp1_cm_set_regamma_pwl( struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) argument
H A Ddcn10_dpp.h1414 const struct pwl_params *params);
1418 const struct pwl_params *params);
1438 struct dc_bias_and_scale *params);
1451 const struct pwl_params *params);
1475 const struct pwl_params *params);
1480 const struct pwl_params *params);
H A Ddcn10_dpp_cm.c434 const struct pwl_params *params)
456 cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
463 const struct pwl_params *params)
485 cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
566 struct dc_bias_and_scale *params)
571 CM_BNS_SCALE_R, params->scale_red,
572 CM_BNS_BIAS_R, params->bias_red);
575 CM_BNS_SCALE_G, params->scale_green,
576 CM_BNS_BIAS_G, params->bias_green);
579 CM_BNS_SCALE_B, params
432 dpp1_cm_program_regamma_luta_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
461 dpp1_cm_program_regamma_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
564 dpp1_program_bias_and_scale( struct dpp *dpp_base, struct dc_bias_and_scale *params) argument
585 dpp1_program_degamma_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
614 dpp1_program_degamma_luta_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
755 dpp1_set_degamma_pwl(struct dpp *dpp_base, const struct pwl_params *params) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp.c370 const struct pwl_params *params,
368 oppn20_dummy_program_regamma_pwl( struct dpp *dpp, const struct pwl_params *params, enum opp_regamma mode) argument
H A Ddcn20_dpp.h714 const struct pwl_params *params);
731 struct dpp *dpp_base, const struct pwl_params *params);
735 const struct pwl_params *params);
739 const struct tetrahedral_params *params);
761 const struct pwl_params *params,
H A Ddcn20_dpp_cm.c118 const struct pwl_params *params)
126 dpp1_program_degamma_lutb_settings(dpp_base, params);
128 dpp1_program_degamma_luta_settings(dpp_base, params);
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a);
443 const struct pwl_params *params)
465 cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
471 const struct pwl_params *params)
493 cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
523 struct dpp *dpp_base, const struct pwl_params *params)
116 dpp2_set_degamma_pwl( struct dpp *dpp_base, const struct pwl_params *params) argument
441 dpp20_program_blnd_luta_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
469 dpp20_program_blnd_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
522 dpp20_program_blnd_lut( struct dpp *dpp_base, const struct pwl_params *params) argument
630 dpp20_program_shaper_luta_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
780 dpp20_program_shaper_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
931 dpp20_program_shaper( struct dpp *dpp_base, const struct pwl_params *params) argument
1115 dpp20_program_3dlut( struct dpp *dpp_base, const struct tetrahedral_params *params) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c703 const struct pwl_params *params)
725 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
731 const struct pwl_params *params)
753 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
788 const struct pwl_params *params)
794 if (params == NULL) {
811 dpp3_program_blnd_luta_settings(dpp_base, params);
813 dpp3_program_blnd_lutb_settings(dpp_base, params);
816 dpp_base, params->rgb_resulted, params
701 dpp3_program_blnd_luta_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
729 dpp3_program_blnd_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
787 dpp3_program_blnd_lut(struct dpp *dpp_base, const struct pwl_params *params) argument
899 dpp3_program_shaper_luta_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
1049 dpp3_program_shaper_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params) argument
1200 dpp3_program_shaper(struct dpp *dpp_base, const struct pwl_params *params) argument
1390 dpp3_program_3dlut(struct dpp *dpp_base, const struct tetrahedral_params *params) argument
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H A Ddcn30_dpp.h589 struct dpp *dpp_base, const struct pwl_params *params);
H A Ddcn30_dpp_cm.c216 struct dpp *dpp_base, const struct pwl_params *params)
225 if (params == NULL) { //bypass if we have no pwl data
293 cm_helper_program_gamcor_xfer_func(dpp_base->ctx, params, &gam_regs);
295 dpp3_program_gammcor_lut(dpp_base, params->rgb_resulted, params->hw_points_num,
215 dpp3_program_gamcor_lut( struct dpp *dpp_base, const struct pwl_params *params) argument
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1197 struct encoder_unblank_param params = { { 0 } }; local
1203 params.timing = pipe_ctx->stream->timing;
1204 params.link_settings.link_rate = link_settings->link_rate;
1207 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1527 struct drr_params params = {0}; local
1598 params.vertical_total_min = stream->adjust.v_total_min;
1599 params.vertical_total_max = stream->adjust.v_total_max;
1602 pipe_ctx->stream_res.tg, &params);
1959 struct drr_params params = {0}; local
1965 params
1995 set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) argument
2099 struct compr_addr_and_pitch_params params = {0, 0, 0}; local
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c3206 struct drr_params params = {0}; local
3212 params.vertical_total_max = adjust.v_total_max;
3213 params.vertical_total_min = adjust.v_total_min;
3214 params.vertical_total_mid = adjust.v_total_mid;
3215 params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
3224 pipe_ctx[i]->stream_res.tg, &params);
3247 int num_pipes, const struct dc_static_screen_params *params)
3252 if (params->triggers.surface_update)
3254 if (params->triggers.cursor_update)
3256 if (params
3246 dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) argument
3876 struct encoder_unblank_param params = {0}; local
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H A Ddcn10_hwseq.h151 int num_pipes, const struct dc_static_screen_params *params);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c821 struct drr_params params = {0}; local
946 params.vertical_total_min = stream->adjust.v_total_min;
947 params.vertical_total_max = stream->adjust.v_total_max;
948 params.vertical_total_mid = stream->adjust.v_total_mid;
949 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
952 pipe_ctx->stream_res.tg, &params);
1014 const struct pwl_params *params = NULL; local
1027 params = &stream->out_transfer_func.pwl;
1033 params = &mpc->blender_params;
1041 * if above if is not executed then 'params' equa
1813 union block_sequence_params params; local
1967 struct bit_depth_reduction_params params; local
2618 struct encoder_unblank_param params = {0}; local
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c592 struct encoder_unblank_param params = { { 0 } }; local
598 params.timing = pipe_ctx->stream->timing;
600 params.link_settings.link_rate = link_settings->link_rate;
605 params.timing.pix_clk_100hz /= 2;
607 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c251 //get the shaper lut params
301 const struct pwl_params *params = NULL; local
314 params = &plane_state->in_transfer_func.pwl;
318 params = &dpp_base->degamma_params;
320 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
376 const struct pwl_params *params = NULL; local
385 params = &stream->out_transfer_func.pwl;
391 params = &mpc->blender_params;
398 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c620 int num_pipes, const struct dc_static_screen_params *params)
625 if (params->triggers.surface_update)
627 if (params->triggers.cursor_update)
629 if (params->triggers.force_trigger)
634 triggers, params->num_frames);
619 dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) argument
H A Ddcn31_hwseq.h60 int num_pipes, const struct dc_static_screen_params *params);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c421 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params) argument
423 struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;
424 bool lock = params->subvp_pipe_control_lock_fast_params.lock;
425 bool subvp_immediate_flip = params->subvp_pipe_control_lock_fast_params.subvp_immediate_flip;
448 //get the shaper lut params
527 const struct pwl_params *params = NULL; local
540 params = &plane_state->in_transfer_func.pwl;
544 params = &dpp_base->degamma_params;
546 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
562 const struct pwl_params *params local
1211 struct encoder_unblank_param params = {0}; local
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H A Ddcn32_hwseq.h87 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c1361 struct drr_params params = {0}; local
1367 params.vertical_total_max = adjust.v_total_max;
1368 params.vertical_total_min = adjust.v_total_min;
1369 params.vertical_total_mid = adjust.v_total_mid;
1370 params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
1388 pipe_ctx[i]->stream_res.tg, &params);
1398 int num_pipes, const struct dc_static_screen_params *params)
1403 if (params->triggers.surface_update)
1405 if (params->triggers.cursor_update)
1407 if (params
1397 dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) argument
1419 struct long_vtotal_params params = {0}; local
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