1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dm_services.h" 27#include "core_types.h" 28#include "reg_helper.h" 29#include "dcn30/dcn30_dpp.h" 30#include "basics/conversion.h" 31#include "dcn30/dcn30_cm_common.h" 32 33#define REG(reg)\ 34 dpp->tf_regs->reg 35 36#define CTX \ 37 dpp->base.ctx 38 39#undef FN 40#define FN(reg_name, field_name) \ 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 42 43 44void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) 45{ 46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 47 uint32_t gamcor_lut_mode, rgam_lut_mode; 48 49 REG_GET(DPP_CONTROL, 50 DPP_CLOCK_ENABLE, &s->is_enabled); 51 52 // Pre-degamma (ROM) 53 REG_GET_2(PRE_DEGAM, 54 PRE_DEGAM_MODE, &s->pre_dgam_mode, 55 PRE_DEGAM_SELECT, &s->pre_dgam_select); 56 57 // Gamma Correction (RAM) 58 REG_GET(CM_GAMCOR_CONTROL, 59 CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode); 60 if (s->gamcor_mode) { 61 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &gamcor_lut_mode); 62 if (!gamcor_lut_mode) 63 s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B 64 } 65 66 // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) 67 REG_GET(CM_SHAPER_CONTROL, 68 CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); 69 REG_GET(CM_3DLUT_MODE, 70 CM_3DLUT_MODE_CURRENT, &s->lut3d_mode); 71 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, 72 CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); 73 REG_GET(CM_3DLUT_MODE, 74 CM_3DLUT_SIZE, &s->lut3d_size); 75 76 // Blend/Out Gamma (RAM) 77 REG_GET(CM_BLNDGAM_CONTROL, 78 CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode); 79 if (s->rgam_lut_mode){ 80 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode); 81 if (!rgam_lut_mode) 82 s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B 83 } 84} 85 86/*program post scaler scs block in dpp CM*/ 87void dpp3_program_post_csc( 88 struct dpp *dpp_base, 89 enum dc_color_space color_space, 90 enum dcn10_input_csc_select input_select, 91 const struct out_csc_color_matrix *tbl_entry) 92{ 93 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 94 int i; 95 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix); 96 const uint16_t *regval = NULL; 97 uint32_t cur_select = 0; 98 enum dcn10_input_csc_select select; 99 struct color_matrices_reg gam_regs; 100 101 if (input_select == INPUT_CSC_SELECT_BYPASS) { 102 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0); 103 return; 104 } 105 106 if (tbl_entry == NULL) { 107 for (i = 0; i < arr_size; i++) 108 if (dpp_input_csc_matrix[i].color_space == color_space) { 109 regval = dpp_input_csc_matrix[i].regval; 110 break; 111 } 112 113 if (regval == NULL) { 114 BREAK_TO_DEBUGGER(); 115 return; 116 } 117 } else { 118 regval = tbl_entry->regval; 119 } 120 121 /* determine which CSC matrix (icsc or coma) we are using 122 * currently. select the alternate set to double buffer 123 * the CSC update so CSC is updated on frame boundary 124 */ 125 REG_GET(CM_POST_CSC_CONTROL, 126 CM_POST_CSC_MODE_CURRENT, &cur_select); 127 128 if (cur_select != INPUT_CSC_SELECT_ICSC) 129 select = INPUT_CSC_SELECT_ICSC; 130 else 131 select = INPUT_CSC_SELECT_COMA; 132 133 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; 134 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; 135 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; 136 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; 137 138 if (select == INPUT_CSC_SELECT_ICSC) { 139 140 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12); 141 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34); 142 143 } else { 144 145 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12); 146 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34); 147 148 } 149 150 cm_helper_program_color_matrices( 151 dpp->base.ctx, 152 regval, 153 &gam_regs); 154 155 REG_SET(CM_POST_CSC_CONTROL, 0, 156 CM_POST_CSC_MODE, select); 157} 158 159 160/*CNVC degam unit has read only LUTs*/ 161void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) 162{ 163 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 164 int pre_degam_en = 1; 165 int degamma_lut_selection = 0; 166 167 switch (tr) { 168 case TRANSFER_FUNCTION_LINEAR: 169 case TRANSFER_FUNCTION_UNITY: 170 pre_degam_en = 0; //bypass 171 break; 172 case TRANSFER_FUNCTION_SRGB: 173 degamma_lut_selection = 0; 174 break; 175 case TRANSFER_FUNCTION_BT709: 176 degamma_lut_selection = 4; 177 break; 178 case TRANSFER_FUNCTION_PQ: 179 degamma_lut_selection = 5; 180 break; 181 case TRANSFER_FUNCTION_HLG: 182 degamma_lut_selection = 6; 183 break; 184 case TRANSFER_FUNCTION_GAMMA22: 185 degamma_lut_selection = 1; 186 break; 187 case TRANSFER_FUNCTION_GAMMA24: 188 degamma_lut_selection = 2; 189 break; 190 case TRANSFER_FUNCTION_GAMMA26: 191 degamma_lut_selection = 3; 192 break; 193 default: 194 pre_degam_en = 0; 195 break; 196 } 197 198 REG_SET_2(PRE_DEGAM, 0, 199 PRE_DEGAM_MODE, pre_degam_en, 200 PRE_DEGAM_SELECT, degamma_lut_selection); 201} 202 203void dpp3_cnv_setup ( 204 struct dpp *dpp_base, 205 enum surface_pixel_format format, 206 enum expansion_mode mode, 207 struct dc_csc_transform input_csc_color_matrix, 208 enum dc_color_space input_color_space, 209 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 210{ 211 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 212 uint32_t pixel_format = 0; 213 uint32_t alpha_en = 1; 214 enum dc_color_space color_space = COLOR_SPACE_SRGB; 215 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS; 216 bool force_disable_cursor = false; 217 uint32_t is_2bit = 0; 218 uint32_t alpha_plane_enable = 0; 219 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; 220 uint32_t realpha_en = 0, realpha_ablnd_en = 0; 221 uint32_t program_prealpha_dealpha = 0; 222 struct out_csc_color_matrix tbl_entry; 223 int i; 224 225 REG_SET_2(FORMAT_CONTROL, 0, 226 CNVC_BYPASS, 0, 227 FORMAT_EXPANSION_MODE, mode); 228 229 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); 230 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); 231 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); 232 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); 233 234 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); 235 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); 236 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); 237 238 switch (format) { 239 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 240 pixel_format = 1; 241 break; 242 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 243 pixel_format = 3; 244 alpha_en = 0; 245 break; 246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 247 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 248 pixel_format = 8; 249 break; 250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 251 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 252 pixel_format = 10; 253 is_2bit = 1; 254 break; 255 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 256 force_disable_cursor = false; 257 pixel_format = 65; 258 color_space = COLOR_SPACE_YCBCR709; 259 select = INPUT_CSC_SELECT_ICSC; 260 break; 261 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 262 force_disable_cursor = true; 263 pixel_format = 64; 264 color_space = COLOR_SPACE_YCBCR709; 265 select = INPUT_CSC_SELECT_ICSC; 266 break; 267 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 268 force_disable_cursor = true; 269 pixel_format = 67; 270 color_space = COLOR_SPACE_YCBCR709; 271 select = INPUT_CSC_SELECT_ICSC; 272 break; 273 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 274 force_disable_cursor = true; 275 pixel_format = 66; 276 color_space = COLOR_SPACE_YCBCR709; 277 select = INPUT_CSC_SELECT_ICSC; 278 break; 279 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 280 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 281 pixel_format = 26; /* ARGB16161616_UNORM */ 282 break; 283 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 284 pixel_format = 24; 285 break; 286 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 287 pixel_format = 25; 288 break; 289 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 290 pixel_format = 12; 291 color_space = COLOR_SPACE_YCBCR709; 292 select = INPUT_CSC_SELECT_ICSC; 293 break; 294 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 295 pixel_format = 112; 296 alpha_en = 0; 297 break; 298 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 299 pixel_format = 113; 300 alpha_en = 0; 301 break; 302 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 303 pixel_format = 114; 304 color_space = COLOR_SPACE_YCBCR709; 305 select = INPUT_CSC_SELECT_ICSC; 306 is_2bit = 1; 307 break; 308 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: 309 pixel_format = 115; 310 color_space = COLOR_SPACE_YCBCR709; 311 select = INPUT_CSC_SELECT_ICSC; 312 is_2bit = 1; 313 break; 314 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 315 pixel_format = 116; 316 alpha_plane_enable = 0; 317 break; 318 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 319 pixel_format = 116; 320 alpha_plane_enable = 1; 321 break; 322 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 323 pixel_format = 118; 324 alpha_en = 0; 325 break; 326 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 327 pixel_format = 119; 328 alpha_en = 0; 329 break; 330 default: 331 break; 332 } 333 334 /* Set default color space based on format if none is given. */ 335 color_space = input_color_space ? input_color_space : color_space; 336 337 if (is_2bit == 1 && alpha_2bit_lut != NULL) { 338 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); 339 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); 340 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); 341 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); 342 } 343 344 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, 345 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, 346 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable); 347 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 348 349 if (program_prealpha_dealpha) { 350 dealpha_en = 1; 351 realpha_en = 1; 352 } 353 REG_SET_2(PRE_DEALPHA, 0, 354 PRE_DEALPHA_EN, dealpha_en, 355 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); 356 REG_SET_2(PRE_REALPHA, 0, 357 PRE_REALPHA_EN, realpha_en, 358 PRE_REALPHA_ABLND_EN, realpha_ablnd_en); 359 360 /* If input adjustment exists, program the ICSC with those values. */ 361 if (input_csc_color_matrix.enable_adjustment == true) { 362 for (i = 0; i < 12; i++) 363 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 364 365 tbl_entry.color_space = input_color_space; 366 367 if (color_space >= COLOR_SPACE_YCBCR601) 368 select = INPUT_CSC_SELECT_ICSC; 369 else 370 select = INPUT_CSC_SELECT_BYPASS; 371 372 dpp3_program_post_csc(dpp_base, color_space, select, 373 &tbl_entry); 374 } else { 375 dpp3_program_post_csc(dpp_base, color_space, select, NULL); 376 } 377 378 if (force_disable_cursor) { 379 REG_UPDATE(CURSOR_CONTROL, 380 CURSOR_ENABLE, 0); 381 REG_UPDATE(CURSOR0_CONTROL, 382 CUR0_ENABLE, 0); 383 } 384} 385 386#define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19)) 387 388void dpp3_set_cursor_attributes( 389 struct dpp *dpp_base, 390 struct dc_cursor_attributes *cursor_attributes) 391{ 392 enum dc_cursor_color_format color_format = cursor_attributes->color_format; 393 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 394 int cur_rom_en = 0; 395 396 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 397 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 398 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) { 399 cur_rom_en = 1; 400 } 401 } 402 403 REG_UPDATE_3(CURSOR0_CONTROL, 404 CUR0_MODE, color_format, 405 CUR0_EXPANSION_MODE, 0, 406 CUR0_ROM_EN, cur_rom_en); 407 408 if (color_format == CURSOR_MODE_MONO) { 409 /* todo: clarify what to program these to */ 410 REG_UPDATE(CURSOR0_COLOR0, 411 CUR0_COLOR0, 0x00000000); 412 REG_UPDATE(CURSOR0_COLOR1, 413 CUR0_COLOR1, 0xFFFFFFFF); 414 } 415 416 dpp_base->att.cur0_ctl.bits.expansion_mode = 0; 417 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en; 418 dpp_base->att.cur0_ctl.bits.mode = color_format; 419} 420 421 422bool dpp3_get_optimal_number_of_taps( 423 struct dpp *dpp, 424 struct scaler_data *scl_data, 425 const struct scaling_taps *in_taps) 426{ 427 int num_part_y, num_part_c; 428 int max_taps_y, max_taps_c; 429 int min_taps_y, min_taps_c; 430 enum lb_memory_config lb_config; 431 432 if (scl_data->viewport.width > scl_data->h_active && 433 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 434 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 435 return false; 436 437 /* 438 * Set default taps if none are provided 439 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling 440 * taps = 4 for upscaling 441 */ 442 if (in_taps->h_taps == 0) { 443 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) 444 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); 445 else 446 scl_data->taps.h_taps = 4; 447 } else 448 scl_data->taps.h_taps = in_taps->h_taps; 449 if (in_taps->v_taps == 0) { 450 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) 451 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); 452 else 453 scl_data->taps.v_taps = 4; 454 } else 455 scl_data->taps.v_taps = in_taps->v_taps; 456 if (in_taps->v_taps_c == 0) { 457 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1) 458 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8); 459 else 460 scl_data->taps.v_taps_c = 4; 461 } else 462 scl_data->taps.v_taps_c = in_taps->v_taps_c; 463 if (in_taps->h_taps_c == 0) { 464 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1) 465 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); 466 else 467 scl_data->taps.h_taps_c = 4; 468 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 469 /* Only 1 and even h_taps_c are supported by hw */ 470 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 471 else 472 scl_data->taps.h_taps_c = in_taps->h_taps_c; 473 474 /*Ensure we can support the requested number of vtaps*/ 475 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); 476 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c); 477 478 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */ 479 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10)) 480 lb_config = LB_MEMORY_CONFIG_3; 481 else 482 lb_config = LB_MEMORY_CONFIG_0; 483 484 dpp->caps->dscl_calc_lb_num_partitions( 485 scl_data, lb_config, &num_part_y, &num_part_c); 486 487 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ 488 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2) 489 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2); 490 else 491 max_taps_y = num_part_y; 492 493 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2) 494 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2); 495 else 496 max_taps_c = num_part_c; 497 498 if (max_taps_y < min_taps_y) 499 return false; 500 else if (max_taps_c < min_taps_c) 501 return false; 502 503 if (scl_data->taps.v_taps > max_taps_y) 504 scl_data->taps.v_taps = max_taps_y; 505 506 if (scl_data->taps.v_taps_c > max_taps_c) 507 scl_data->taps.v_taps_c = max_taps_c; 508 509 if (!dpp->ctx->dc->debug.always_scale) { 510 if (IDENTITY_RATIO(scl_data->ratios.horz)) 511 scl_data->taps.h_taps = 1; 512 if (IDENTITY_RATIO(scl_data->ratios.vert)) 513 scl_data->taps.v_taps = 1; 514 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 515 scl_data->taps.h_taps_c = 1; 516 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 517 scl_data->taps.v_taps_c = 1; 518 } 519 520 return true; 521} 522 523static void dpp3_deferred_update(struct dpp *dpp_base) 524{ 525 int bypass_state; 526 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 527 528 if (dpp_base->deferred_reg_writes.bits.disable_dscl) { 529 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3); 530 dpp_base->deferred_reg_writes.bits.disable_dscl = false; 531 } 532 533 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) { 534 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state); 535 if (bypass_state == 0) { // only program if bypass was latched 536 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3); 537 } else 538 ASSERT(0); // LUT select was updated again before vupdate 539 dpp_base->deferred_reg_writes.bits.disable_gamcor = false; 540 } 541 542 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) { 543 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state); 544 if (bypass_state == 0) { // only program if bypass was latched 545 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3); 546 } else 547 ASSERT(0); // LUT select was updated again before vupdate 548 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false; 549 } 550 551 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) { 552 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state); 553 if (bypass_state == 0) { // only program if bypass was latched 554 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3); 555 } else 556 ASSERT(0); // LUT select was updated again before vupdate 557 dpp_base->deferred_reg_writes.bits.disable_3dlut = false; 558 } 559 560 if (dpp_base->deferred_reg_writes.bits.disable_shaper) { 561 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state); 562 if (bypass_state == 0) { // only program if bypass was latched 563 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3); 564 } else 565 ASSERT(0); // LUT select was updated again before vupdate 566 dpp_base->deferred_reg_writes.bits.disable_shaper = false; 567 } 568} 569 570static void dpp3_power_on_blnd_lut( 571 struct dpp *dpp_base, 572 bool power_on) 573{ 574 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 575 576 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 577 if (power_on) { 578 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0); 579 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5); 580 } else { 581 dpp_base->ctx->dc->optimized_required = true; 582 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; 583 } 584 } else { 585 REG_SET(CM_MEM_PWR_CTRL, 0, 586 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1); 587 } 588} 589 590static void dpp3_power_on_hdr3dlut( 591 struct dpp *dpp_base, 592 bool power_on) 593{ 594 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 595 596 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 597 if (power_on) { 598 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0); 599 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5); 600 } else { 601 dpp_base->ctx->dc->optimized_required = true; 602 dpp_base->deferred_reg_writes.bits.disable_3dlut = true; 603 } 604 } 605} 606 607static void dpp3_power_on_shaper( 608 struct dpp *dpp_base, 609 bool power_on) 610{ 611 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 612 613 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 614 if (power_on) { 615 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0); 616 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5); 617 } else { 618 dpp_base->ctx->dc->optimized_required = true; 619 dpp_base->deferred_reg_writes.bits.disable_shaper = true; 620 } 621 } 622} 623 624static void dpp3_configure_blnd_lut( 625 struct dpp *dpp_base, 626 bool is_ram_a) 627{ 628 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 629 630 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL, 631 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7, 632 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1); 633 634 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); 635} 636 637static void dpp3_program_blnd_pwl( 638 struct dpp *dpp_base, 639 const struct pwl_result_data *rgb, 640 uint32_t num) 641{ 642 uint32_t i; 643 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 644 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg; 645 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg; 646 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg; 647 648 if (is_rgb_equal(rgb, num)) { 649 for (i = 0 ; i < num; i++) 650 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 651 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 652 } else { 653 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); 654 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4); 655 for (i = 0 ; i < num; i++) 656 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 657 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 658 659 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); 660 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2); 661 for (i = 0 ; i < num; i++) 662 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); 663 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green); 664 665 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); 666 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1); 667 for (i = 0 ; i < num; i++) 668 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); 669 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue); 670 } 671} 672 673static void dcn3_dpp_cm_get_reg_field( 674 struct dcn3_dpp *dpp, 675 struct dcn3_xfer_func_reg *reg) 676{ 677 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 678 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 679 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 680 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 681 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 682 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 683 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 684 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 685 686 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 687 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 688 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 689 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 690 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 691 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 692 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 693 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 694 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 695 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 696 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 697 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 698} 699 700/*program blnd lut RAM A*/ 701static void dpp3_program_blnd_luta_settings( 702 struct dpp *dpp_base, 703 const struct pwl_params *params) 704{ 705 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 706 struct dcn3_xfer_func_reg gam_regs; 707 708 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 709 710 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); 711 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); 712 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); 713 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B); 714 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G); 715 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R); 716 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); 717 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); 718 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); 719 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); 720 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); 721 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); 722 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); 723 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); 724 725 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 726} 727 728/*program blnd lut RAM B*/ 729static void dpp3_program_blnd_lutb_settings( 730 struct dpp *dpp_base, 731 const struct pwl_params *params) 732{ 733 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 734 struct dcn3_xfer_func_reg gam_regs; 735 736 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 737 738 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); 739 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); 740 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); 741 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B); 742 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G); 743 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R); 744 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); 745 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); 746 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); 747 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); 748 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); 749 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); 750 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); 751 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); 752 753 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 754} 755 756static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base) 757{ 758 enum dc_lut_mode mode; 759 uint32_t mode_current = 0; 760 uint32_t in_use = 0; 761 762 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 763 764 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current); 765 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use); 766 767 switch (mode_current) { 768 case 0: 769 case 1: 770 mode = LUT_BYPASS; 771 break; 772 773 case 2: 774 if (in_use == 0) 775 mode = LUT_RAM_A; 776 else 777 mode = LUT_RAM_B; 778 break; 779 default: 780 mode = LUT_BYPASS; 781 break; 782 } 783 784 return mode; 785} 786 787static bool dpp3_program_blnd_lut(struct dpp *dpp_base, 788 const struct pwl_params *params) 789{ 790 enum dc_lut_mode current_mode; 791 enum dc_lut_mode next_mode; 792 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 793 794 if (params == NULL) { 795 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0); 796 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 797 dpp3_power_on_blnd_lut(dpp_base, false); 798 return false; 799 } 800 801 current_mode = dpp3_get_blndgam_current(dpp_base); 802 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B) 803 next_mode = LUT_RAM_A; 804 else 805 next_mode = LUT_RAM_B; 806 807 dpp3_power_on_blnd_lut(dpp_base, true); 808 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A); 809 810 if (next_mode == LUT_RAM_A) 811 dpp3_program_blnd_luta_settings(dpp_base, params); 812 else 813 dpp3_program_blnd_lutb_settings(dpp_base, params); 814 815 dpp3_program_blnd_pwl( 816 dpp_base, params->rgb_resulted, params->hw_points_num); 817 818 REG_UPDATE_2(CM_BLNDGAM_CONTROL, 819 CM_BLNDGAM_MODE, 2, 820 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1); 821 822 return true; 823} 824 825 826static void dpp3_program_shaper_lut( 827 struct dpp *dpp_base, 828 const struct pwl_result_data *rgb, 829 uint32_t num) 830{ 831 uint32_t i, red, green, blue; 832 uint32_t red_delta, green_delta, blue_delta; 833 uint32_t red_value, green_value, blue_value; 834 835 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 836 837 for (i = 0 ; i < num; i++) { 838 839 red = rgb[i].red_reg; 840 green = rgb[i].green_reg; 841 blue = rgb[i].blue_reg; 842 843 red_delta = rgb[i].delta_red_reg; 844 green_delta = rgb[i].delta_green_reg; 845 blue_delta = rgb[i].delta_blue_reg; 846 847 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); 848 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); 849 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); 850 851 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); 852 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); 853 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); 854 } 855 856} 857 858static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base) 859{ 860 enum dc_lut_mode mode; 861 uint32_t state_mode; 862 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 863 864 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode); 865 866 switch (state_mode) { 867 case 0: 868 mode = LUT_BYPASS; 869 break; 870 case 1: 871 mode = LUT_RAM_A; 872 break; 873 case 2: 874 mode = LUT_RAM_B; 875 break; 876 default: 877 mode = LUT_BYPASS; 878 break; 879 } 880 881 return mode; 882} 883 884static void dpp3_configure_shaper_lut( 885 struct dpp *dpp_base, 886 bool is_ram_a) 887{ 888 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 889 890 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 891 CM_SHAPER_LUT_WRITE_EN_MASK, 7); 892 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 893 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 894 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); 895} 896 897/*program shaper RAM A*/ 898 899static void dpp3_program_shaper_luta_settings( 900 struct dpp *dpp_base, 901 const struct pwl_params *params) 902{ 903 const struct gamma_curve *curve; 904 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 905 906 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, 907 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 908 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 909 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, 910 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 911 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0); 912 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, 913 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 914 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0); 915 916 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, 917 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 918 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 919 920 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, 921 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 922 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 923 924 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, 925 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 926 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 927 928 curve = params->arr_curve_points; 929 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, 930 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 931 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 932 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 933 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 934 935 curve += 2; 936 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, 937 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, 938 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 939 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, 940 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 941 942 curve += 2; 943 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, 944 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, 945 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 946 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, 947 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 948 949 curve += 2; 950 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, 951 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, 952 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 953 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, 954 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 955 956 curve += 2; 957 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, 958 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, 959 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 960 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, 961 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 962 963 curve += 2; 964 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, 965 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, 966 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 967 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, 968 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 969 970 curve += 2; 971 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, 972 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, 973 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 974 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, 975 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 976 977 curve += 2; 978 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, 979 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, 980 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 981 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, 982 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 983 984 curve += 2; 985 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, 986 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, 987 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 988 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, 989 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 990 991 curve += 2; 992 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, 993 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, 994 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 995 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, 996 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 997 998 curve += 2; 999 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0, 1000 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, 1001 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 1002 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, 1003 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 1004 1005 curve += 2; 1006 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0, 1007 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, 1008 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 1009 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, 1010 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 1011 1012 curve += 2; 1013 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0, 1014 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, 1015 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 1016 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, 1017 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 1018 1019 curve += 2; 1020 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0, 1021 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, 1022 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 1023 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, 1024 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 1025 1026 curve += 2; 1027 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0, 1028 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, 1029 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 1030 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, 1031 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 1032 1033 curve += 2; 1034 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0, 1035 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, 1036 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 1037 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, 1038 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 1039 1040 curve += 2; 1041 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0, 1042 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, 1043 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 1044 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, 1045 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 1046} 1047 1048/*program shaper RAM B*/ 1049static void dpp3_program_shaper_lutb_settings( 1050 struct dpp *dpp_base, 1051 const struct pwl_params *params) 1052{ 1053 const struct gamma_curve *curve; 1054 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1055 1056 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, 1057 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 1058 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); 1059 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, 1060 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 1061 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0); 1062 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, 1063 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 1064 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0); 1065 1066 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, 1067 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 1068 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 1069 1070 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, 1071 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 1072 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 1073 1074 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, 1075 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 1076 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 1077 1078 curve = params->arr_curve_points; 1079 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, 1080 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1081 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1082 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1083 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1084 1085 curve += 2; 1086 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, 1087 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, 1088 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 1089 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, 1090 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 1091 1092 curve += 2; 1093 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, 1094 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, 1095 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 1096 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, 1097 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 1098 1099 curve += 2; 1100 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, 1101 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, 1102 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 1103 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, 1104 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 1105 1106 curve += 2; 1107 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0, 1108 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, 1109 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 1110 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, 1111 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 1112 1113 curve += 2; 1114 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0, 1115 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, 1116 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 1117 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, 1118 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 1119 1120 curve += 2; 1121 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0, 1122 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, 1123 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 1124 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, 1125 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 1126 1127 curve += 2; 1128 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0, 1129 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, 1130 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 1131 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, 1132 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 1133 1134 curve += 2; 1135 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0, 1136 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, 1137 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 1138 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, 1139 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 1140 1141 curve += 2; 1142 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0, 1143 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, 1144 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 1145 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, 1146 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 1147 1148 curve += 2; 1149 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0, 1150 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, 1151 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 1152 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, 1153 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 1154 1155 curve += 2; 1156 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0, 1157 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, 1158 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 1159 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, 1160 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 1161 1162 curve += 2; 1163 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0, 1164 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, 1165 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 1166 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, 1167 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 1168 1169 curve += 2; 1170 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0, 1171 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, 1172 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 1173 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, 1174 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 1175 1176 curve += 2; 1177 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0, 1178 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, 1179 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 1180 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, 1181 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 1182 1183 curve += 2; 1184 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0, 1185 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, 1186 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 1187 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, 1188 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 1189 1190 curve += 2; 1191 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0, 1192 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, 1193 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 1194 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, 1195 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 1196 1197} 1198 1199 1200static bool dpp3_program_shaper(struct dpp *dpp_base, 1201 const struct pwl_params *params) 1202{ 1203 enum dc_lut_mode current_mode; 1204 enum dc_lut_mode next_mode; 1205 1206 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1207 1208 if (params == NULL) { 1209 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); 1210 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1211 dpp3_power_on_shaper(dpp_base, false); 1212 return false; 1213 } 1214 1215 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1216 dpp3_power_on_shaper(dpp_base, true); 1217 1218 current_mode = dpp3_get_shaper_current(dpp_base); 1219 1220 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) 1221 next_mode = LUT_RAM_B; 1222 else 1223 next_mode = LUT_RAM_A; 1224 1225 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A); 1226 1227 if (next_mode == LUT_RAM_A) 1228 dpp3_program_shaper_luta_settings(dpp_base, params); 1229 else 1230 dpp3_program_shaper_lutb_settings(dpp_base, params); 1231 1232 dpp3_program_shaper_lut( 1233 dpp_base, params->rgb_resulted, params->hw_points_num); 1234 1235 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); 1236 1237 return true; 1238 1239} 1240 1241static enum dc_lut_mode get3dlut_config( 1242 struct dpp *dpp_base, 1243 bool *is_17x17x17, 1244 bool *is_12bits_color_channel) 1245{ 1246 uint32_t i_mode, i_enable_10bits, lut_size; 1247 enum dc_lut_mode mode; 1248 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1249 1250 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, 1251 CM_3DLUT_30BIT_EN, &i_enable_10bits); 1252 REG_GET(CM_3DLUT_MODE, 1253 CM_3DLUT_MODE_CURRENT, &i_mode); 1254 1255 switch (i_mode) { 1256 case 0: 1257 mode = LUT_BYPASS; 1258 break; 1259 case 1: 1260 mode = LUT_RAM_A; 1261 break; 1262 case 2: 1263 mode = LUT_RAM_B; 1264 break; 1265 default: 1266 mode = LUT_BYPASS; 1267 break; 1268 } 1269 if (i_enable_10bits > 0) 1270 *is_12bits_color_channel = false; 1271 else 1272 *is_12bits_color_channel = true; 1273 1274 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); 1275 1276 if (lut_size == 0) 1277 *is_17x17x17 = true; 1278 else 1279 *is_17x17x17 = false; 1280 1281 return mode; 1282} 1283/* 1284 * select ramA or ramB, or bypass 1285 * select color channel size 10 or 12 bits 1286 * select 3dlut size 17x17x17 or 9x9x9 1287 */ 1288static void dpp3_set_3dlut_mode( 1289 struct dpp *dpp_base, 1290 enum dc_lut_mode mode, 1291 bool is_color_channel_12bits, 1292 bool is_lut_size17x17x17) 1293{ 1294 uint32_t lut_mode; 1295 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1296 1297 if (mode == LUT_BYPASS) 1298 lut_mode = 0; 1299 else if (mode == LUT_RAM_A) 1300 lut_mode = 1; 1301 else 1302 lut_mode = 2; 1303 1304 REG_UPDATE_2(CM_3DLUT_MODE, 1305 CM_3DLUT_MODE, lut_mode, 1306 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); 1307} 1308 1309static void dpp3_select_3dlut_ram( 1310 struct dpp *dpp_base, 1311 enum dc_lut_mode mode, 1312 bool is_color_channel_12bits) 1313{ 1314 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1315 1316 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL, 1317 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, 1318 CM_3DLUT_30BIT_EN, 1319 is_color_channel_12bits == true ? 0:1); 1320} 1321 1322 1323 1324static void dpp3_set3dlut_ram12( 1325 struct dpp *dpp_base, 1326 const struct dc_rgb *lut, 1327 uint32_t entries) 1328{ 1329 uint32_t i, red, green, blue, red1, green1, blue1; 1330 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1331 1332 for (i = 0 ; i < entries; i += 2) { 1333 red = lut[i].red<<4; 1334 green = lut[i].green<<4; 1335 blue = lut[i].blue<<4; 1336 red1 = lut[i+1].red<<4; 1337 green1 = lut[i+1].green<<4; 1338 blue1 = lut[i+1].blue<<4; 1339 1340 REG_SET_2(CM_3DLUT_DATA, 0, 1341 CM_3DLUT_DATA0, red, 1342 CM_3DLUT_DATA1, red1); 1343 1344 REG_SET_2(CM_3DLUT_DATA, 0, 1345 CM_3DLUT_DATA0, green, 1346 CM_3DLUT_DATA1, green1); 1347 1348 REG_SET_2(CM_3DLUT_DATA, 0, 1349 CM_3DLUT_DATA0, blue, 1350 CM_3DLUT_DATA1, blue1); 1351 1352 } 1353} 1354 1355/* 1356 * load selected lut with 10 bits color channels 1357 */ 1358static void dpp3_set3dlut_ram10( 1359 struct dpp *dpp_base, 1360 const struct dc_rgb *lut, 1361 uint32_t entries) 1362{ 1363 uint32_t i, red, green, blue, value; 1364 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1365 1366 for (i = 0; i < entries; i++) { 1367 red = lut[i].red; 1368 green = lut[i].green; 1369 blue = lut[i].blue; 1370 1371 value = (red<<20) | (green<<10) | blue; 1372 1373 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); 1374 } 1375 1376} 1377 1378 1379static void dpp3_select_3dlut_ram_mask( 1380 struct dpp *dpp_base, 1381 uint32_t ram_selection_mask) 1382{ 1383 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1384 1385 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, 1386 ram_selection_mask); 1387 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); 1388} 1389 1390static bool dpp3_program_3dlut(struct dpp *dpp_base, 1391 const struct tetrahedral_params *params) 1392{ 1393 enum dc_lut_mode mode; 1394 bool is_17x17x17; 1395 bool is_12bits_color_channel; 1396 const struct dc_rgb *lut0; 1397 const struct dc_rgb *lut1; 1398 const struct dc_rgb *lut2; 1399 const struct dc_rgb *lut3; 1400 int lut_size0; 1401 int lut_size; 1402 1403 if (params == NULL) { 1404 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); 1405 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1406 dpp3_power_on_hdr3dlut(dpp_base, false); 1407 return false; 1408 } 1409 1410 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1411 dpp3_power_on_hdr3dlut(dpp_base, true); 1412 1413 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); 1414 1415 if (mode == LUT_BYPASS || mode == LUT_RAM_B) 1416 mode = LUT_RAM_A; 1417 else 1418 mode = LUT_RAM_B; 1419 1420 is_17x17x17 = !params->use_tetrahedral_9; 1421 is_12bits_color_channel = params->use_12bits; 1422 if (is_17x17x17) { 1423 lut0 = params->tetrahedral_17.lut0; 1424 lut1 = params->tetrahedral_17.lut1; 1425 lut2 = params->tetrahedral_17.lut2; 1426 lut3 = params->tetrahedral_17.lut3; 1427 lut_size0 = sizeof(params->tetrahedral_17.lut0)/ 1428 sizeof(params->tetrahedral_17.lut0[0]); 1429 lut_size = sizeof(params->tetrahedral_17.lut1)/ 1430 sizeof(params->tetrahedral_17.lut1[0]); 1431 } else { 1432 lut0 = params->tetrahedral_9.lut0; 1433 lut1 = params->tetrahedral_9.lut1; 1434 lut2 = params->tetrahedral_9.lut2; 1435 lut3 = params->tetrahedral_9.lut3; 1436 lut_size0 = sizeof(params->tetrahedral_9.lut0)/ 1437 sizeof(params->tetrahedral_9.lut0[0]); 1438 lut_size = sizeof(params->tetrahedral_9.lut1)/ 1439 sizeof(params->tetrahedral_9.lut1[0]); 1440 } 1441 1442 dpp3_select_3dlut_ram(dpp_base, mode, 1443 is_12bits_color_channel); 1444 dpp3_select_3dlut_ram_mask(dpp_base, 0x1); 1445 if (is_12bits_color_channel) 1446 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0); 1447 else 1448 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0); 1449 1450 dpp3_select_3dlut_ram_mask(dpp_base, 0x2); 1451 if (is_12bits_color_channel) 1452 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size); 1453 else 1454 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size); 1455 1456 dpp3_select_3dlut_ram_mask(dpp_base, 0x4); 1457 if (is_12bits_color_channel) 1458 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size); 1459 else 1460 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size); 1461 1462 dpp3_select_3dlut_ram_mask(dpp_base, 0x8); 1463 if (is_12bits_color_channel) 1464 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size); 1465 else 1466 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size); 1467 1468 1469 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, 1470 is_17x17x17); 1471 1472 return true; 1473} 1474static struct dpp_funcs dcn30_dpp_funcs = { 1475 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, 1476 .dpp_read_state = dpp30_read_state, 1477 .dpp_reset = dpp_reset, 1478 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 1479 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, 1480 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap, 1481 .dpp_set_csc_adjustment = NULL, 1482 .dpp_set_csc_default = NULL, 1483 .dpp_program_regamma_pwl = NULL, 1484 .dpp_set_pre_degam = dpp3_set_pre_degam, 1485 .dpp_program_input_lut = NULL, 1486 .dpp_full_bypass = dpp1_full_bypass, 1487 .dpp_setup = dpp3_cnv_setup, 1488 .dpp_program_degamma_pwl = NULL, 1489 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha, 1490 .dpp_program_cm_bias = dpp3_program_cm_bias, 1491 .dpp_program_blnd_lut = dpp3_program_blnd_lut, 1492 .dpp_program_shaper_lut = dpp3_program_shaper, 1493 .dpp_program_3dlut = dpp3_program_3dlut, 1494 .dpp_deferred_update = dpp3_deferred_update, 1495 .dpp_program_bias_and_scale = NULL, 1496 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, 1497 .set_cursor_attributes = dpp3_set_cursor_attributes, 1498 .set_cursor_position = dpp1_set_cursor_position, 1499 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 1500 .dpp_dppclk_control = dpp1_dppclk_control, 1501 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, 1502 .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap, 1503}; 1504 1505 1506static struct dpp_caps dcn30_dpp_cap = { 1507 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, 1508 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, 1509}; 1510 1511bool dpp3_construct( 1512 struct dcn3_dpp *dpp, 1513 struct dc_context *ctx, 1514 uint32_t inst, 1515 const struct dcn3_dpp_registers *tf_regs, 1516 const struct dcn3_dpp_shift *tf_shift, 1517 const struct dcn3_dpp_mask *tf_mask) 1518{ 1519 dpp->base.ctx = ctx; 1520 1521 dpp->base.inst = inst; 1522 dpp->base.funcs = &dcn30_dpp_funcs; 1523 dpp->base.caps = &dcn30_dpp_cap; 1524 1525 dpp->tf_regs = tf_regs; 1526 dpp->tf_shift = tf_shift; 1527 dpp->tf_mask = tf_mask; 1528 1529 return true; 1530} 1531 1532