/linux-master/arch/x86/mm/ |
H A D | amdtopology.c | 81 u64 base, limit; local 83 base = read_pci_config(0, nb, 1, 0x40 + i*8); 87 if ((base & 3) == 0) { 94 base, limit); 99 pr_info("Skipping node entry %d (base %Lx)\n", 100 i, base); 103 if ((base >> 8) & 3 || (limit >> 8) & 3) { 105 nodeid, (base >> 8) & 3, (limit >> 8) & 3); 120 if (limit <= base) 123 base >> [all...] |
/linux-master/drivers/phy/st/ |
H A D | phy-miphy28lp.c | 205 void __iomem *base; member in struct:miphy28lp_phy 367 void __iomem *base = miphy_phy->base; local 371 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); 374 writeb_relaxed(val, base + MIPHY_CONF_RESET); 376 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); 381 writeb_relaxed(val, base + MIPHY_CONTROL); 384 writeb_relaxed(val, base + MIPHY_CONTROL); 391 void __iomem *base = miphy_phy->base; local 432 void __iomem *base = miphy_phy->base; local 459 void __iomem *base = miphy_phy->base; local 499 void __iomem *base = miphy_phy->base; local 527 void __iomem *base = miphy_phy->base; local 555 void __iomem *base = miphy_phy->base; local 593 void __iomem *base = miphy_phy->base; local 639 void __iomem *base = miphy_phy->base; local 683 void __iomem *base = miphy_phy->base; local 720 void __iomem *base = miphy_phy->base; local 845 miphy28lp_get_one_addr(struct device *dev, struct device_node *child, char *rname, void __iomem **base) argument [all...] |
/linux-master/sound/soc/codecs/ |
H A D | cs35l56.c | 92 ret = pm_runtime_resume_and_get(cs35l56->base.dev); 99 ret = regmap_bulk_read(cs35l56->base.regmap, CS35L56_ASP1TX1_INPUT, 102 pm_runtime_mark_last_busy(cs35l56->base.dev); 103 pm_runtime_put_autosuspend(cs35l56->base.dev); 106 dev_err(cs35l56->base.dev, "Failed to read ASP1 mixer regs: %d\n", ret); 120 dev_warn(cs35l56->base.dev, "Could not find control %s\n", name); 149 ret = regmap_read(cs35l56->base.regmap, addr, &val); 179 ret = regmap_update_bits_check(cs35l56->base.regmap, addr, 292 return cs35l56_force_sync_asp1_registers_from_cache(&cs35l56->base); 306 dev_dbg(cs35l56->base [all...] |
/linux-master/drivers/gpu/drm/nouveau/ |
H A D | nv10_fence.c | 38 PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno); 62 nouveau_fence_context_del(&fctx->base); 65 nouveau_fence_context_free(&fctx->base); 77 nouveau_fence_context_new(chan, &fctx->base); 78 fctx->base.emit = nv10_fence_emit; 79 fctx->base.read = nv10_fence_read; 80 fctx->base.sync = nv10_fence_sync; 105 priv->base.dtor = nv10_fence_destroy; 106 priv->base.context_new = nv10_fence_context_new; 107 priv->base [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/ce/ |
H A D | gp100.c | 49 gp100_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) argument 53 u32 stat = nvkm_rd32(device, 0x104418 + base); 64 const u32 base = subdev->inst * 0x80; local 65 u32 mask = nvkm_rd32(device, 0x10440c + base); 66 u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; 69 nvkm_wr32(device, 0x104410 + base, 0x00000001); 74 nvkm_wr32(device, 0x104410 + base, 0x00000002); 78 gp100_ce_intr_launcherr(ce, base); 79 nvkm_wr32(device, 0x104410 + base, 0x00000004); 84 nvkm_wr32(device, 0x104410 + base, int [all...] |
/linux-master/drivers/clk/ |
H A D | clk-moxart.c | 18 void __iomem *base; local 28 base = of_iomap(node, 0); 29 if (!base) { 34 mul = readl(base + 0x30) >> 3 & 0x3f; 35 iounmap(base); 57 void __iomem *base; local 68 base = of_iomap(node, 0); 69 if (!base) { 74 val = readl(base + 0xc) >> 4 & 0x7; 75 iounmap(base); [all...] |
/linux-master/drivers/misc/ |
H A D | sram-exec.c | 25 unsigned long base = (unsigned long)part->base; local 26 unsigned long end = base + block->size; 28 if (!PAGE_ALIGNED(base) || !PAGE_ALIGNED(end)) { 77 unsigned long base; local 95 base = (unsigned long)part->base; 100 ret = set_memory_nx((unsigned long)base, pages); 103 ret = set_memory_rw((unsigned long)base, pages); 109 ret = set_memory_rox((unsigned long)base, page [all...] |
/linux-master/arch/arm64/crypto/ |
H A D | sha512-glue.c | 60 .base.cra_name = "sha512", 61 .base.cra_driver_name = "sha512-arm64", 62 .base.cra_priority = 150, 63 .base.cra_blocksize = SHA512_BLOCK_SIZE, 64 .base.cra_module = THIS_MODULE, 72 .base.cra_name = "sha384", 73 .base.cra_driver_name = "sha384-arm64", 74 .base.cra_priority = 150, 75 .base.cra_blocksize = SHA384_BLOCK_SIZE, 76 .base [all...] |
/linux-master/drivers/gpu/drm/hisilicon/kirin/ |
H A D | kirin_drm_ade.c | 43 void __iomem *base; member in struct:ade_hw_ctx 94 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) argument 101 ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, 105 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) argument 112 tmp = readl(base + ADE_RELOAD_DIS(reg_num)); 118 void __iomem *base = ctx->base; local 121 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST, 124 writel(0, base + ADE_OVLY1_TRANS_CFG); 125 writel(0, base 174 void __iomem *base = ctx->base; local 248 void __iomem *base = ctx->base; local 279 void __iomem *base = ctx->base; local 294 void __iomem *base = ctx->base; local 309 void __iomem *base = ctx->base; local 327 void __iomem *base = ctx->base; local 348 ade_rdma_dump_regs(void __iomem *base, u32 ch) argument 376 ade_clip_dump_regs(void __iomem *base, u32 ch) argument 390 ade_compositor_routing_dump_regs(void __iomem *base, u32 ch) argument 403 ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp) argument 415 ade_dump_regs(void __iomem *base) argument 435 ade_dump_regs(void __iomem *base) argument 507 void __iomem *base = ctx->base; local 548 ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb, u32 ch, u32 y, u32 in_h, u32 fmt) argument 582 ade_rdma_disable(void __iomem *base, u32 ch) argument 592 ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x, u32 in_w, u32 in_h) argument 621 ade_clip_disable(void __iomem *base, u32 ch) argument 662 ade_compositor_routing_set(void __iomem *base, u8 ch, u32 x0, u32 y0, u32 in_w, u32 in_h, u32 fmt) argument 693 ade_compositor_routing_disable(void __iomem *base, u32 ch) argument 715 void __iomem *base = ctx->base; local 744 void __iomem *base = ctx->base; local [all...] |
/linux-master/net/sunrpc/ |
H A D | socklib.c | 84 * @base: starting offset 90 xdr_partial_copy_from_skb(struct xdr_buf *xdr, unsigned int base, struct xdr_skb_reader *desc, xdr_skb_read_actor copy_actor) argument 98 if (base < len) { 99 len -= base; 100 ret = copy_actor(desc, (char *)xdr->head[0].iov_base + base, len); 104 base = 0; 106 base -= len; 110 if (unlikely(base >= pglen)) { 111 base -= pglen; 114 if (base || xd 221 xprt_send_pagedata(struct socket *sock, struct msghdr *msg, struct xdr_buf *xdr, size_t base) argument 234 xprt_send_rm_and_kvec(struct socket *sock, struct msghdr *msg, rpc_fraghdr marker, struct kvec *vec, size_t base) argument 264 xprt_sock_sendmsg(struct socket *sock, struct msghdr *msg, struct xdr_buf *xdr, unsigned int base, rpc_fraghdr marker, unsigned int *sent_p) argument [all...] |
/linux-master/drivers/net/ethernet/mellanox/mlxbf_gige/ |
H A D | mlxbf_gige_rx.c | 17 void __iomem *base = priv->base; local 21 writeq(dmac, base + MLXBF_GIGE_RX_MAC_FILTER + 25 control = readq(base + MLXBF_GIGE_CONTROL); 27 writeq(control, base + MLXBF_GIGE_CONTROL); 33 void __iomem *base = priv->base; local 36 *dmac = readq(base + MLXBF_GIGE_RX_MAC_FILTER + 42 void __iomem *base = priv->base; local 61 void __iomem *base = priv->base; local [all...] |
/linux-master/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
H A D | dpu_10_0_sm8650.h | 23 .base = 0, .len = 0x494, 34 .base = 0x15000, .len = 0x1000, 39 .base = 0x16000, .len = 0x1000, 44 .base = 0x17000, .len = 0x1000, 49 .base = 0x18000, .len = 0x1000, 54 .base = 0x19000, .len = 0x1000, 59 .base = 0x1a000, .len = 0x1000, 68 .base = 0x4000, .len = 0x344, 75 .base = 0x6000, .len = 0x344, 82 .base [all...] |
/linux-master/arch/arm/mach-shmobile/ |
H A D | setup-rcar-gen2.c | 64 void __iomem *base; local 99 base = ioremap(0xe6080000, PAGE_SIZE); 108 if ((ioread32(base + CNTCR) & 1) == 0 || 109 ioread32(base + CNTFID0) != freq) { 111 iowrite32(freq, base + CNTFID0); 115 iowrite32(1, base + CNTCR); 118 iounmap(base); 127 u64 base, size; member in struct:memory_reserve_config 151 u64 base, size; local 153 base [all...] |
/linux-master/arch/mips/kernel/ |
H A D | vdso.c | 74 unsigned long base = STACK_TOP; local 78 base += PAGE_SIZE; 82 base += get_random_u32_below(VDSO_RANDOMIZE_SIZE); 83 base = PAGE_ALIGN(base); 86 return base; 93 unsigned long gic_size, vvar_size, size, base, data_addr, vdso_addr, gic_pfn, gic_base; local 102 base = mmap_region(NULL, STACK_TOP, PAGE_SIZE, 106 if (IS_ERR_VALUE(base)) { 107 ret = base; [all...] |
/linux-master/drivers/power/reset/ |
H A D | gemini-poweroff.c | 33 void __iomem *base; member in struct:gemini_powercon 42 val = readl(gpw->base + GEMINI_PWC_CTRLREG); 44 writel(val, gpw->base + GEMINI_PWC_CTRLREG); 46 val = readl(gpw->base + GEMINI_PWC_STATREG); 79 val = readl(gpw->base + GEMINI_PWC_CTRLREG); 81 writel(val, gpw->base + GEMINI_PWC_CTRLREG); 85 writel(val, gpw->base + GEMINI_PWC_CTRLREG); 102 gpw->base = devm_platform_ioremap_resource(pdev, 0); 103 if (IS_ERR(gpw->base)) 104 return PTR_ERR(gpw->base); [all...] |
/linux-master/arch/x86/crypto/ |
H A D | twofish_glue_3way.c | 24 return twofish_setkey(&tfm->base, key, keylen); 78 .base.cra_name = "ecb(twofish)", 79 .base.cra_driver_name = "ecb-twofish-3way", 80 .base.cra_priority = 300, 81 .base.cra_blocksize = TF_BLOCK_SIZE, 82 .base.cra_ctxsize = sizeof(struct twofish_ctx), 83 .base.cra_module = THIS_MODULE, 90 .base.cra_name = "cbc(twofish)", 91 .base.cra_driver_name = "cbc-twofish-3way", 92 .base [all...] |
/linux-master/drivers/irqchip/ |
H A D | irq-gic-common.c | 48 void __iomem *base, void (*sync_access)(void)) 61 val = oldval = readl_relaxed(base + confoff); 81 writel_relaxed(val, base + confoff); 82 if (readl_relaxed(base + confoff) != val) 93 void gic_dist_config(void __iomem *base, int gic_irqs, argument 103 base + GIC_DIST_CONFIG + i / 4); 109 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); 117 base + GIC_DIST_ACTIVE_CLEAR + i / 8); 119 base + GIC_DIST_ENABLE_CLEAR + i / 8); 126 void gic_cpu_config(void __iomem *base, in argument 47 gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | gm20b.c | 105 * base.n is now the *integer* part of the N factor. 109 struct gk20a_pll base; member in struct:gm20b_pll 121 struct gk20a_clk base; member in struct:gm20b_clk 139 #define gm20b_clk(p) container_of((gk20a_clk(p)), struct gm20b_clk, base) 162 struct nvkm_subdev *subdev = &clk->base.base.subdev; 166 gk20a_pllg_read_mnp(&clk->base, &pll->base); 175 struct nvkm_device *device = clk->base.base 464 gm20b_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) argument 572 gm20b_clk_prog(struct nvkm_clk *base) argument 720 gm20b_clk_fini(struct nvkm_clk *base) argument 811 gm20b_clk_init(struct nvkm_clk *base) argument [all...] |
/linux-master/arch/arm/mach-s3c/ |
H A D | pm-gpio.c | 29 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); 30 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); 35 void __iomem *base = chip->base; local 36 u32 old_gpcon = __raw_readl(base + OFFS_CON); 37 u32 old_gpdat = __raw_readl(base + OFFS_DAT); 48 __raw_writel(gpcon, base + OFFS_CON); 52 __raw_writel(gps_gpdat, base + OFFS_DAT); 53 __raw_writel(gps_gpcon, base + OFFS_CON); 66 chip->pm_save[0] = __raw_readl(chip->base 122 void __iomem *base = chip->base; local 258 void __iomem *base = chip->base; local [all...] |
/linux-master/drivers/i3c/master/mipi-i3c-hci/ |
H A D | ext_caps.c | 24 static int hci_extcap_hardware_id(struct i3c_hci *hci, void __iomem *base) argument 26 hci->vendor_mipi_id = readl(base + 0x04); 27 hci->vendor_version_id = readl(base + 0x08); 28 hci->vendor_product_id = readl(base + 0x0c); 45 static int hci_extcap_master_config(struct i3c_hci *hci, void __iomem *base) argument 47 u32 master_config = readl(base + 0x04); 59 static int hci_extcap_multi_bus(struct i3c_hci *hci, void __iomem *base) argument 61 u32 bus_instance = readl(base + 0x04); 68 static int hci_extcap_xfer_modes(struct i3c_hci *hci, void __iomem *base) argument 70 u32 header = readl(base); 88 hci_extcap_xfer_rates(struct i3c_hci *hci, void __iomem *base) argument 116 hci_extcap_auto_command(struct i3c_hci *hci, void __iomem *base) argument 130 hci_extcap_debug(struct i3c_hci *hci, void __iomem *base) argument 137 hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base) argument 144 hci_extcap_non_curr_master(struct i3c_hci *hci, void __iomem *base) argument 151 hci_extcap_ccc_resp_conf(struct i3c_hci *hci, void __iomem *base) argument 157 hci_extcap_global_DAT(struct i3c_hci *hci, void __iomem *base) argument 163 hci_extcap_multilane(struct i3c_hci *hci, void __iomem *base) argument 169 hci_extcap_ncm_multilane(struct i3c_hci *hci, void __iomem *base) argument 201 hci_extcap_vendor_NXP(struct i3c_hci *hci, void __iomem *base) argument 226 hci_extcap_vendor_specific(struct i3c_hci *hci, void __iomem *base, u32 cap_id, u32 cap_length) argument [all...] |
/linux-master/drivers/phy/mediatek/ |
H A D | phy-mtk-hdmi-mt8173.c | 90 void __iomem *base = hdmi_phy->regs; local 92 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 93 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); 94 mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN); 95 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 97 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); 99 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 100 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 108 void __iomem *base = hdmi_phy->regs; local 110 mtk_phy_clear_bits(base 139 void __iomem *base = hdmi_phy->regs; local [all...] |
/linux-master/drivers/watchdog/ |
H A D | davinci_wdt.c | 60 * @base - base io address of WD device 65 void __iomem *base; member in struct:davinci_wdt_device 80 iowrite32(0, davinci_wdt->base + TCR); 82 iowrite32(0, davinci_wdt->base + TGCR); 84 iowrite32(tgcr, davinci_wdt->base + TGCR); 86 iowrite32(0, davinci_wdt->base + TIM12); 87 iowrite32(0, davinci_wdt->base + TIM34); 90 iowrite32(timer_margin, davinci_wdt->base + PRD12); 92 iowrite32(timer_margin, davinci_wdt->base [all...] |
/linux-master/arch/x86/boot/ |
H A D | string.c | 118 * @base: The number base to use 120 unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base) argument 124 if (!base) 125 base = simple_guess_base(cp); 127 if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x') 134 if (value >= base) 136 result = result * base + value; 145 long simple_strtol(const char *cp, char **endp, unsigned int base) argument 148 return -simple_strtoull(cp + 1, endp, base); 232 _parse_integer_fixup_radix(const char *s, unsigned int *base) argument 256 _parse_integer(const char *s, unsigned int base, unsigned long long *p) argument 295 _kstrtoull(const char *s, unsigned int base, unsigned long long *res) argument 331 kstrtoull(const char *s, unsigned int base, unsigned long long *res) argument 338 _kstrtoul(const char *s, unsigned int base, unsigned long *res) argument 367 boot_kstrtoul(const char *s, unsigned int base, unsigned long *res) argument [all...] |
/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_modeset_setup.c | 38 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 40 to_intel_crtc_state(crtc->base.state); 51 to_intel_plane_state(plane->base.state); 61 crtc->base.base.id, crtc->base.name); 76 ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base); 87 crtc->base.base.id, crtc->base [all...] |
/linux-master/drivers/block/ |
H A D | swim.c | 63 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v)) 64 #define swim_read(base, reg) in_8(&(base)->read_##reg) 87 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) 88 #define iwm_read(base, reg) in_8(&(base)->reg) 211 struct swim __iomem *base; member in struct:swim_priv 217 extern int swim_read_sector_header(struct swim __iomem *base, 223 set_swim_mode(struct swim __iomem *base, int enable) argument 248 get_swim_mode(struct swim __iomem *base) argument 270 swim_select(struct swim __iomem *base, int sel) argument 279 swim_action(struct swim __iomem *base, int action) argument 295 swim_readbit(struct swim __iomem *base, int bit) argument 308 swim_drive(struct swim __iomem *base, enum drive_location location) argument 320 swim_motor(struct swim __iomem *base, enum motor_action action) argument 341 swim_eject(struct swim __iomem *base) argument 357 swim_head(struct swim __iomem *base, enum head head) argument 367 swim_step(struct swim __iomem *base) argument 385 swim_track00(struct swim __iomem *base) argument 407 swim_seek(struct swim __iomem *base, int step) argument 428 struct swim __iomem *base = fs->swd->base; local 445 struct swim __iomem *base = fs->swd->base; local 461 struct swim __iomem *base = fs->swd->base; local 498 struct swim __iomem *base = fs->swd->base; local 585 struct swim __iomem *base = fs->swd->base; local 614 struct swim __iomem *base = fs->swd->base; local 674 struct swim __iomem *base = fs->swd->base; local 751 struct swim __iomem *base = swd->base; local 792 struct swim __iomem *base = swd->base; local [all...] |