1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R-Car Generation 2 support 4 * 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Magnus Damm 7 * Copyright (C) 2014 Ulrich Hecht 8 */ 9 10#include <linux/clocksource.h> 11#include <linux/device.h> 12#include <linux/dma-map-ops.h> 13#include <linux/io.h> 14#include <linux/kernel.h> 15#include <linux/memblock.h> 16#include <linux/of.h> 17#include <linux/of_clk.h> 18#include <linux/of_fdt.h> 19#include <linux/psci.h> 20#include <asm/mach/arch.h> 21#include <asm/secure_cntvoff.h> 22#include "common.h" 23#include "rcar-gen2.h" 24 25static const struct of_device_id cpg_matches[] __initconst = { 26 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" }, 27 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" }, 28 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" }, 29 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" }, 30 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" }, 31 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" }, 32 { /* sentinel */ } 33}; 34 35static unsigned int __init get_extal_freq(void) 36{ 37 const struct of_device_id *match; 38 struct device_node *cpg, *extal; 39 u32 freq = 20000000; 40 int idx = 0; 41 42 cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match); 43 if (!cpg) 44 return freq; 45 46 if (match->data) 47 idx = of_property_match_string(cpg, "clock-names", match->data); 48 extal = of_parse_phandle(cpg, "clocks", idx); 49 of_node_put(cpg); 50 if (!extal) 51 return freq; 52 53 of_property_read_u32(extal, "clock-frequency", &freq); 54 of_node_put(extal); 55 return freq; 56} 57 58#define CNTCR 0 59#define CNTFID0 0x20 60 61static void __init rcar_gen2_timer_init(void) 62{ 63 bool need_update = true; 64 void __iomem *base; 65 u32 freq; 66 67 /* 68 * If PSCI is available then most likely we are running on PSCI-enabled 69 * U-Boot which, we assume, has already taken care of resetting CNTVOFF 70 * and updating counter module before switching to non-secure mode 71 * and we don't need to. 72 */ 73#ifdef CONFIG_ARM_PSCI_FW 74 if (psci_ops.cpu_on) 75 need_update = false; 76#endif 77 78 if (need_update == false) 79 goto skip_update; 80 81 secure_cntvoff_init(); 82 83 if (of_machine_is_compatible("renesas,r8a7745") || 84 of_machine_is_compatible("renesas,r8a77470") || 85 of_machine_is_compatible("renesas,r8a7792") || 86 of_machine_is_compatible("renesas,r8a7794")) { 87 freq = 260000000 / 8; /* ZS / 8 */ 88 } else { 89 /* At Linux boot time the r8a7790 arch timer comes up 90 * with the counter disabled. Moreover, it may also report 91 * a potentially incorrect fixed 13 MHz frequency. To be 92 * correct these registers need to be updated to use the 93 * frequency EXTAL / 2. 94 */ 95 freq = get_extal_freq() / 2; 96 } 97 98 /* Remap "armgcnt address map" space */ 99 base = ioremap(0xe6080000, PAGE_SIZE); 100 101 /* 102 * Update the timer if it is either not running, or is not at the 103 * right frequency. The timer is only configurable in secure mode 104 * so this avoids an abort if the loader started the timer and 105 * entered the kernel in non-secure mode. 106 */ 107 108 if ((ioread32(base + CNTCR) & 1) == 0 || 109 ioread32(base + CNTFID0) != freq) { 110 /* Update registers with correct frequency */ 111 iowrite32(freq, base + CNTFID0); 112 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); 113 114 /* make sure arch timer is started by setting bit 0 of CNTCR */ 115 iowrite32(1, base + CNTCR); 116 } 117 118 iounmap(base); 119 120skip_update: 121 of_clk_init(NULL); 122 timer_probe(); 123} 124 125struct memory_reserve_config { 126 u64 reserved; 127 u64 base, size; 128}; 129 130static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname, 131 int depth, void *data) 132{ 133 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 134 const __be32 *reg, *endp; 135 int l; 136 struct memory_reserve_config *mrc = data; 137 u64 lpae_start = 1ULL << 32; 138 139 /* We are scanning "memory" nodes only */ 140 if (type == NULL || strcmp(type, "memory")) 141 return 0; 142 143 reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); 144 if (reg == NULL) 145 reg = of_get_flat_dt_prop(node, "reg", &l); 146 if (reg == NULL) 147 return 0; 148 149 endp = reg + (l / sizeof(__be32)); 150 while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { 151 u64 base, size; 152 153 base = dt_mem_next_cell(dt_root_addr_cells, ®); 154 size = dt_mem_next_cell(dt_root_size_cells, ®); 155 156 if (base >= lpae_start) 157 continue; 158 159 if ((base + size) >= lpae_start) 160 size = lpae_start - base; 161 162 if (size < mrc->reserved) 163 continue; 164 165 if (base < mrc->base) 166 continue; 167 168 /* keep the area at top near the 32-bit legacy limit */ 169 mrc->base = base + size - mrc->reserved; 170 mrc->size = mrc->reserved; 171 } 172 173 return 0; 174} 175 176static void __init rcar_gen2_reserve(void) 177{ 178 struct memory_reserve_config mrc; 179 180 /* reserve 256 MiB at the top of the physical legacy 32-bit space */ 181 memset(&mrc, 0, sizeof(mrc)); 182 mrc.reserved = SZ_256M; 183 184 of_scan_flat_dt(rcar_gen2_scan_mem, &mrc); 185#ifdef CONFIG_DMA_CMA 186 if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) { 187 static struct cma *rcar_gen2_dma_contiguous; 188 189 dma_contiguous_reserve_area(mrc.size, mrc.base, 0, 190 &rcar_gen2_dma_contiguous, true); 191 } 192#endif 193} 194 195static const char * const rcar_gen2_boards_compat_dt[] __initconst = { 196 "renesas,r8a7790", 197 "renesas,r8a7791", 198 "renesas,r8a7792", 199 "renesas,r8a7793", 200 "renesas,r8a7794", 201 NULL 202}; 203 204DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)") 205 .init_late = shmobile_init_late, 206 .init_time = rcar_gen2_timer_init, 207 .reserve = rcar_gen2_reserve, 208 .dt_compat = rcar_gen2_boards_compat_dt, 209MACHINE_END 210 211static const char * const rz_g1_boards_compat_dt[] __initconst = { 212 "renesas,r8a7742", 213 "renesas,r8a7743", 214 "renesas,r8a7744", 215 "renesas,r8a7745", 216 "renesas,r8a77470", 217 NULL 218}; 219 220DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)") 221 .init_late = shmobile_init_late, 222 .init_time = rcar_gen2_timer_init, 223 .reserve = rcar_gen2_reserve, 224 .dt_compat = rz_g1_boards_compat_dt, 225MACHINE_END 226