Searched refs:reg_offset (Results 26 - 50 of 374) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4.c40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0];
167 uint32_t reg_offset,
177 if (sdma_v4_4_ras_fields[i].reg_offset != reg_offset)
202 uint32_t reg_offset = 0; local
204 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER);
205 reg_value = RREG32(reg_offset);
211 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2);
212 reg_value = RREG32(reg_offset);
239 uint32_t reg_offset; local
166 sdma_v4_4_get_ras_error_count(struct amdgpu_device *adev, uint32_t reg_offset, uint32_t value, uint32_t instance, uint32_t *sec_count) argument
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H A Dsoc15.h57 uint32_t reg_offset; member in struct:soc15_reg
64 uint32_t reg_offset; member in struct:soc15_reg_entry
74 uint32_t reg_offset; member in struct:soc15_allowed_register_entry
83 uint32_t reg_offset; member in struct:soc15_ras_field_entry
92 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
H A Dmmsch_v4_0.h68 uint32_t reg_offset : 28; member in struct:mmsch_v4_0_cmd_direct_reg_header
73 uint32_t reg_offset : 20; member in struct:mmsch_v4_0_cmd_indirect_reg_header
107 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
118 direct_wt.cmd_header.reg_offset = reg; \
128 direct_poll.cmd_header.reg_offset = reg; \
H A Dmmsch_v2_0.h245 uint32_t reg_offset : 28; member in struct:mmsch_v2_0_cmd_direct_reg_header
250 uint32_t reg_offset : 20; member in struct:mmsch_v2_0_cmd_indirect_reg_header
283 uint32_t reg_offset,
286 direct_wt->cmd_header.reg_offset = reg_offset;
293 uint32_t reg_offset,
296 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
305 uint32_t reg_offset,
308 direct_poll->cmd_header.reg_offset
281 mmsch_v2_0_insert_direct_wt(struct mmsch_v2_0_cmd_direct_write *direct_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t value) argument
291 mmsch_v2_0_insert_direct_rd_mod_wt(struct mmsch_v2_0_cmd_direct_read_modify_write *direct_rd_mod_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t data) argument
303 mmsch_v2_0_insert_direct_poll(struct mmsch_v2_0_cmd_direct_polling *direct_poll, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t wait) argument
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/linux-master/drivers/mfd/
H A Drk8xx-core.c258 .reg_offset = 0,
262 .reg_offset = 0,
266 .reg_offset = 0,
270 .reg_offset = 0,
274 .reg_offset = 0,
278 .reg_offset = 0,
282 .reg_offset = 0,
286 .reg_offset = 0,
315 .reg_offset = 0,
319 .reg_offset
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H A Dtps65090.c90 .reg_offset = 1,
94 .reg_offset = 1,
98 .reg_offset = 1,
102 .reg_offset = 1,
106 .reg_offset = 1,
110 .reg_offset = 1,
114 .reg_offset = 1,
118 .reg_offset = 1,
H A Dhi655x-pmic.c24 { .reg_offset = 0, .mask = OTMP_D1R_INT_MASK },
25 { .reg_offset = 0, .mask = VSYS_2P5_R_INT_MASK },
26 { .reg_offset = 0, .mask = VSYS_UV_D3R_INT_MASK },
27 { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT_MASK },
28 { .reg_offset = 0, .mask = PWRON_D4SR_INT_MASK },
29 { .reg_offset = 0, .mask = PWRON_D20F_INT_MASK },
30 { .reg_offset = 0, .mask = PWRON_D20R_INT_MASK },
31 { .reg_offset = 0, .mask = RESERVE_INT_MASK },
H A Dmax77693.c113 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
114 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
115 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },
116 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
118 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
119 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },
120 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
121 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
122 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
123 { .reg_offset
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H A Dda9150-core.c258 .reg_offset = 0,
262 .reg_offset = 0,
266 .reg_offset = 0,
270 .reg_offset = 0,
274 .reg_offset = 0,
278 .reg_offset = 1,
282 .reg_offset = 1,
286 .reg_offset = 1,
290 .reg_offset = 1,
294 .reg_offset
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H A Dwm5110-tables.c310 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
311 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
312 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
313 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
316 .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
319 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
322 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
325 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
331 .reg_offset
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H A Dda9062-core.c31 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
35 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
39 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
44 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
48 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
52 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
56 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
61 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
65 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
69 .reg_offset
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H A Dmax77686.c116 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, },
117 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, },
118 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, },
119 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, },
120 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, },
121 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, },
122 { .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, },
123 { .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, },
125 { .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, },
126 { .reg_offset
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H A D88pm805.c98 .reg_offset = 1,
102 .reg_offset = 1,
106 .reg_offset = 1,
110 .reg_offset = 1,
114 .reg_offset = 1,
118 .reg_offset = 1,
/linux-master/drivers/clk/qcom/
H A Dclk-regmap-mux-div.h15 * @reg_offset: offset of the mux/divider register
28 u32 reg_offset; member in struct:clk_regmap_mux_div
/linux-master/arch/powerpc/include/asm/
H A Dtsi108.h103 static inline u32 tsi108_read_reg(u32 reg_offset) argument
105 return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
108 static inline void tsi108_write_reg(u32 reg_offset, u32 val) argument
110 out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
/linux-master/drivers/gpu/drm/radeon/
H A Dni_dma.c191 u32 reg_offset, wb_offset; local
197 reg_offset = DMA0_REGISTER_OFFSET;
201 reg_offset = DMA1_REGISTER_OFFSET;
205 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
206 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
214 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
217 WREG32(DMA_RB_RPTR + reg_offset, 0);
218 WREG32(DMA_RB_WPTR + reg_offset, 0);
221 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
223 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
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/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c85 unsigned int reg_offset; member in struct:rockchip_emmc_phy
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
112 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
165 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
178 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
188 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
194 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
226 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
289 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
296 rk_phy->reg_offset
354 unsigned int reg_offset; local
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/linux-master/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom.h24 const u32 *reg_offset; member in struct:qcom_smmu_config
H A Darm-smmu-qcom-debug.c29 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS],
35 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK],
41 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR],
/linux-master/drivers/gpu/drm/gma500/
H A Dintel_gmbus.c254 int i, reg_offset; local
260 reg_offset = 0;
262 GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
269 GMBUS_REG_WRITE(GMBUS1 + reg_offset,
275 GMBUS_REG_READ(GMBUS2+reg_offset);
279 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
282 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
285 val = GMBUS_REG_READ(GMBUS3 + reg_offset);
299 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
300 GMBUS_REG_WRITE(GMBUS1 + reg_offset,
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/linux-master/drivers/extcon/
H A Dextcon-sm5502.c208 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_ATTACH_MASK, },
209 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_DETACH_MASK, },
210 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_KP_MASK, },
211 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKP_MASK, },
212 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKR_MASK, },
213 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_EVENT_MASK, },
214 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OCP_EVENT_MASK, },
215 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_OCP_DIS_MASK, },
218 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_VBUS_DET_MASK,},
219 { .reg_offset
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/linux-master/drivers/pwm/
H A Dpwm-mediatek.c40 const unsigned int *reg_offset; member in struct:pwm_mediatek_of_data
115 writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
291 .reg_offset = mtk_pwm_reg_offset_v1,
298 .reg_offset = mtk_pwm_reg_offset_v1,
305 .reg_offset = mtk_pwm_reg_offset_v1,
312 .reg_offset = mtk_pwm_reg_offset_v1,
319 .reg_offset = mtk_pwm_reg_offset_v1,
326 .reg_offset = mtk_pwm_reg_offset_v1,
333 .reg_offset = mtk_pwm_reg_offset_v2,
340 .reg_offset
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/linux-master/drivers/input/misc/
H A Diqs7222.c797 int reg_offset; member in struct:iqs7222_prop_desc
811 .reg_offset = 0,
819 .reg_offset = 0,
827 .reg_offset = 1,
835 .reg_offset = 1,
842 .reg_offset = 1,
849 .reg_offset = 1,
856 .reg_offset = 1,
865 .reg_offset = 2,
872 .reg_offset
2072 int reg_offset = iqs7222_props[i].reg_offset; local
2458 int count, error, reg_offset, i; local
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/linux-master/drivers/comedi/drivers/
H A Dcomedi_8254.c131 unsigned int reg_offset = (reg * I8254_IO8) << i8254->regshift; local
134 outb(val, iobase + reg_offset);
137 return inb(iobase + reg_offset);
145 unsigned int reg_offset = (reg * I8254_IO16) << i8254->regshift; local
148 outw(val, iobase + reg_offset);
151 return inw(iobase + reg_offset);
159 unsigned int reg_offset = (reg * I8254_IO32) << i8254->regshift; local
162 outl(val, iobase + reg_offset);
165 return inl(iobase + reg_offset);
175 unsigned int reg_offset local
189 unsigned int reg_offset = (reg * I8254_IO16) << i8254->regshift; local
203 unsigned int reg_offset = (reg * I8254_IO32) << i8254->regshift; local
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/linux-master/drivers/reset/
H A Dreset-simple.c108 * @reg_offset: offset between base address and first reset register.
117 u32 reg_offset; member in struct:reset_simple_devdata
126 .reg_offset = 0x20,
166 u32 reg_offset = 0; local
186 reg_offset = devdata->reg_offset;
193 data->membase += reg_offset;

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