Lines Matching refs:reg_offset
191 u32 reg_offset, wb_offset;
197 reg_offset = DMA0_REGISTER_OFFSET;
201 reg_offset = DMA1_REGISTER_OFFSET;
205 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
206 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
214 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
217 WREG32(DMA_RB_RPTR + reg_offset, 0);
218 WREG32(DMA_RB_WPTR + reg_offset, 0);
221 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
223 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
229 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
236 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
238 dma_cntl = RREG32(DMA_CNTL + reg_offset);
240 WREG32(DMA_CNTL + reg_offset, dma_cntl);
243 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
245 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);