/haiku/src/system/libroot/os/arch/sparc/ |
H A D | fpu_reg.S | 33 .macro ld32 reg 35 ld [%o0], %f\reg 38 .macro st32 reg 40 st %f\reg, [%o0] 43 .macro ld64 reg 45 ldd [%o0], %f\reg 48 .macro st64 reg 50 std %f\reg, [%o0]
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/haiku/headers/private/kernel/arch/arm/ |
H A D | arch_uart_pl011.h | 40 void Out32(int reg, uint32 value); 41 uint32 In32(int reg);
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H A D | arch_uart_8250_omap.h | 30 virtual void Out8(int reg, uint8 value); 31 virtual uint8 In8(int reg);
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/haiku/src/system/boot/platform/efi/arch/arm64/ |
H A D | aarch64.h | 197 uint64 reg = _arch_mmu_get_tcr(); local 199 return 64 - (reg & T0SZ_MASK); 207 uint64 reg = _arch_mmu_get_tcr(); local 208 return ((reg >> TCR_TG0_SHIFT) & TG_MASK); 221 uint64 reg = _arch_mmu_get_tcr(); local 222 return 64 - ((reg & T1SZ_MASK) >> TCR_T1SZ_SHIFT); 228 uint64 reg = _arch_mmu_get_tcr(); local 229 return ((reg >> TCR_TG1_SHIFT) & TG_MASK);
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/haiku/src/add-ons/kernel/drivers/network/ether/pegasus/ |
H A D | if_aue.c | 49 #define AUE_SETBIT(sc, reg, x) \ 50 aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x)) 52 #define AUE_CLRBIT(sc, reg, x) \ 53 aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x)) 56 aue_csr_read_1(pegasus_dev *sc, int reg) argument 68 AUE_UR_READREG, 0, reg, 1, &val, &length); 79 aue_csr_read_2(pegasus_dev *sc, int reg) argument 91 AUE_UR_READREG, 0, reg, 103 aue_csr_write_1(pegasus_dev *sc, int reg, int val) argument 126 aue_csr_write_2(pegasus_dev *sc, int reg, int val) argument 202 aue_miibus_readreg(pegasus_dev *sc, int phy, int reg) argument 246 aue_miibus_writereg(pegasus_dev *sc, int phy, int reg, int data) argument 272 aue_miibus_read(pegasus_dev *dev, uint16 reg) argument 279 aue_miibus_write(pegasus_dev *dev, uint16 reg, uint16 value) argument [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ |
H A D | ah_decode.h | 36 reg : 24; member in struct:athregrec
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/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8192c/usb/ |
H A D | r92cu_led.c | 56 uint8_t reg; local 59 reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 61 reg |= R92C_LEDCFG0_DIS; 62 rtwn_write_1(sc, R92C_LEDCFG0, reg);
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H A D | r92cu_init.c | 89 uint32_t reg; local 113 reg = rtwn_read_1(sc, R92C_LDOV12D_CTRL); 114 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 116 reg | R92C_LDOV12D_CTRL_LDV12_EN)); 185 uint32_t reg; local 266 reg = rtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 267 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 268 rtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 273 reg 331 uint32_t reg; local [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/syskonnect/dev/sk/ |
H A D | if_skreg.h | 147 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 150 #define SK_REG(reg) ((reg) & SK_REG_MASK) 177 #define SK_IF_READ_4(sc_if, skip, reg) \ 178 sk_win_read_4(sc_if->sk_softc, reg + \ 180 #define SK_IF_READ_2(sc_if, skip, reg) \ 181 sk_win_read_2(sc_if->sk_softc, reg + \ 183 #define SK_IF_READ_1(sc_if, skip, reg) \ 184 sk_win_read_1(sc_if->sk_softc, reg 1432 int reg; member in struct:sk_bcom_hack [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ |
H A D | ar5212_gpio.c | 35 #define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */ 76 uint32_t reg; local 80 reg = OS_REG_READ(ah, AR_GPIODO); 81 reg &= ~(1 << gpio); 82 reg |= (val&1) << gpio; 84 OS_REG_WRITE(ah, AR_GPIODO, reg);
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ |
H A D | ar5315_gpio.c | 34 #define AR5315_GPIOD_MASK 0x0000007F /* GPIO data reg r/w mask */ 76 uint32_t reg; local 81 reg = OS_REG_READ(ah, gpioOffset+AR5315_GPIODO); 82 reg &= ~(1 << gpio); 83 reg |= (val&1) << gpio; 85 OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODO, reg);
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro1000/dev/e1000/ |
H A D | e1000_82542.c | 442 * @reg: e1000 register to be read 449 u32 e1000_translate_register_82542(u32 reg) argument 457 switch (reg) { 459 reg = 0x00040; 462 reg = 0x00108; 465 reg = 0x00110; 468 reg = 0x00114; 471 reg = 0x00118; 474 reg = 0x00120; 477 reg [all...] |
/haiku/src/add-ons/kernel/drivers/audio/emuxki/ |
H A D | io.c | 78 emuxki_chan_read(device_config *config, uint16 chano, uint32 reg) argument 83 ptr = ((((uint32) reg) << 16) & 86 if (reg & 0xff000000) { 87 size = (reg >> 24) & 0x3f; 88 offset = (reg >> 16) & 0x1f; 98 uint32 reg, uint32 data) 103 ptr = ((((uint32) reg) << 16) & 106 if (reg & 0xff000000) { 107 size = (reg >> 24) & 0x3f; 108 offset = (reg >> 1 97 emuxki_chan_write(device_config *config, uint16 chano, uint32 reg, uint32 data) argument 232 emuxki_p16v_read(device_config *config, uint16 chano, uint16 reg) argument 240 emuxki_p16v_write(device_config *config, uint16 chano, uint16 reg, uint32 data) argument [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ |
H A D | ar5416_gpio.c | 88 uint32_t gpio_shift, reg; local 126 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT); 127 reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift); 128 reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift; 129 OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg); 141 uint32_t gpio_shift, reg; local 151 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT); 152 reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift); 153 reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift; 154 OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg); 165 uint32_t reg; local [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/pcnet/dev/mii/ |
H A D | nsphy.c | 149 int reg; local 156 reg = PHY_READ(sc, MII_NSPHY_PCR); 162 reg |= PCR_LED4MODE; 169 reg |= PCR_CIMDIS; 175 reg |= PCR_FLINK100; 187 reg |= 0x0100 | 0x0400; 190 PHY_WRITE(sc, MII_NSPHY_PCR, reg); 290 int reg, i; local 293 reg = BMCR_RESET; 295 reg [all...] |
/haiku/src/bin/fwcontrol/ |
H A D | fwcrom.c | 126 struct csrreg *reg; local 130 reg = crom_get(cc); 131 if ((reg->key & CSRTYPE_MASK) == CSRTYPE_D) { 139 ptr->dir = (struct csrdirectory *) (reg + reg->val); 166 struct csrreg *reg; local 169 reg = crom_get(cc); 170 if (reg->key == key) 171 return reg; 180 struct csrreg *reg; local 207 struct csrreg *reg; local 318 struct csrreg *reg; local 431 struct csrreg reg; member in union:__anon111 525 struct csrreg *reg; local [all...] |
/haiku/src/system/kernel/platform/atari_m68k/ |
H A D | platform.cpp | 106 uint8 ReadReg(uint32 reg) { return in8(fBase + reg); }; argument 107 void WriteReg(uint32 reg, uint8 v) { out8(v, fBase + reg); }; argument 126 uint8 ReadReg(uint32 reg); 127 void WriteReg(uint32 reg, uint8 v) { out8((uint8)reg,fBase+1); out8(v,fBase+3); }; argument 156 virtual uint8 ReadRTCReg(uint8 reg); 157 virtual void WriteRTCReg(uint8 reg, uint8 val); 213 uint32 reg local 227 uint32 reg = Base() + ((irq > 8) ? (MFP_IERA) : (MFP_IERB)); local 241 uint32 reg = Base() + ((irq > 8) ? (MFP_ISRA) : (MFP_ISRB)); local 271 ReadReg(uint32 reg) argument 602 ReadRTCReg(uint8 reg) argument 614 WriteRTCReg(uint8 reg, uint8 val) argument [all...] |
/haiku/src/add-ons/kernel/drivers/audio/ac97/ |
H A D | ac97.c | 43 bool ac97_reg_is_valid(ac97_dev *dev, uint8 reg); 109 bool ad1819_set_rate(ac97_dev *dev, uint8 reg, uint32 rate); 110 bool ad1819_get_rate(ac97_dev *dev, uint8 reg, uint32 *rate); 358 ac97_reg_cached_write(ac97_dev *dev, uint8 reg, uint16 value) argument 360 if (!ac97_reg_is_valid(dev, reg)) 362 dev->reg_write(dev->cookie, reg, value); 363 dev->reg_cache[reg] = value; 368 ac97_reg_cached_read(ac97_dev *dev, uint8 reg) argument 370 if (!ac97_reg_is_valid(dev, reg)) 372 return dev->reg_cache[reg]; 376 ac97_reg_uncached_write(ac97_dev *dev, uint8 reg, uint16 value) argument 385 ac97_reg_uncached_read(ac97_dev *dev, uint8 reg) argument 394 ac97_reg_update(ac97_dev *dev, uint8 reg, uint16 value) argument 406 ac97_reg_update_bits(ac97_dev *dev, uint8 reg, uint16 mask, uint16 value) argument 424 int reg; local 431 ac97_set_rate(ac97_dev *dev, uint8 reg, uint32 rate) argument 466 ac97_get_rate(ac97_dev *dev, uint8 reg, uint32 *rate) argument 680 ac97_reg_is_valid(ac97_dev *dev, uint8 reg) argument 756 ad1819_set_rate(ac97_dev *dev, uint8 reg, uint32 rate) argument 786 ad1819_get_rate(ac97_dev *dev, uint8 reg, uint32 *rate) argument [all...] |
H A D | ac97.h | 189 typedef uint16 (* codec_reg_read)(void * cookie, uint8 reg); 190 typedef void (* codec_reg_write)(void * cookie, uint8 reg, uint16 value); 191 typedef bool (* codec_set_rate)(ac97_dev *dev, uint8 reg, uint32 rate); 192 typedef bool (* codec_get_rate)(ac97_dev *dev, uint8 reg, uint32 *rate); 228 void ac97_reg_cached_write(ac97_dev *dev, uint8 reg, uint16 value); 229 uint16 ac97_reg_cached_read(ac97_dev *dev, uint8 reg); 230 void ac97_reg_uncached_write(ac97_dev *dev, uint8 reg, uint16 value); 231 uint16 ac97_reg_uncached_read(ac97_dev *dev, uint8 reg); 233 bool ac97_reg_update(ac97_dev *dev, uint8 reg, uint16 value); 234 bool ac97_reg_update_bits(ac97_dev *dev, uint8 reg, uint1 265 uint8 reg; member in struct:_ac97_source_info [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8192c/ |
H A D | r92c_chan.c | 161 uint32_t reg; local 165 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 166 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]); 167 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 168 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 169 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]); 170 reg = RW(reg, R92C_TXAGC_A_CCK5 [all...] |
H A D | r92c_rf.c | 59 uint32_t reg[R92C_MAX_CHAINS], val; local 61 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 63 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 66 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 70 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 75 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
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/haiku/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/ |
H A D | if_anreg.h | 50 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->port_res, reg, val) 52 #define CSR_READ_2(sc, reg) bus_read_2(sc->port_res, reg) 54 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->port_res, reg, val) 56 #define CSR_READ_1(sc, reg) bus_read_1(sc->port_res, reg) 61 #define CSR_MEM_WRITE_2(sc, reg, val) bus_write_2(sc->mem_res, reg, va [all...] |
/haiku/src/add-ons/accelerants/skeleton/engine/ |
H A D | info.c | 15 uint16 MacroTablePtr; /* ptr to list with items containing multiple 32bit reg writes */ 42 static void log_pll(uint32 reg, uint32 freq); 46 static status_t translate_ISA_PCI(uint32* reg); 416 uint32 reg, data, data2, and_out, or_in; local 439 reg = *((uint32*)(&(rom[adress]))); 444 LOG(8,("cmd 'calculate indirect and set PLL 32bit reg $%08x for %.3fMHz'\n", 445 reg, ((float)data2))); 451 ENG_RG32(reg) = ((p << 16) | (n << 8) | m); 453 log_pll(reg, data2); 467 reg 784 log_pll(uint32 reg, uint32 freq) argument 928 uint32 reg, reg2, data, data2, and_out, and_out2, or_in, or_in2, safe32, offset32, size32; local 1748 uint32 reg, and_out, and_out2, offset32; local 1908 translate_ISA_PCI(uint32* reg) argument [all...] |
/haiku/src/add-ons/kernel/drivers/dvb/cx23882/ |
H A D | cx22702.h | 31 status_t cx22702_reg_write(i2c_bus *bus, uint8 reg, uint8 data); 32 status_t cx22702_reg_read(i2c_bus *bus, uint8 reg, uint8 *data);
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/haiku/headers/private/kernel/arch/generic/ |
H A D | debug_uart.h | 43 virtual void Out8(int reg, uint8 value); 44 virtual uint8 In8(int reg);
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