1/*-
2 * Copyright (c) 2002 by Thomas Moestl <tmm@FreeBSD.org>.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26
27/*
28 * Define arrays of leaf functions to load/store fp registers to memory. See
29 * fpu_reg.h for the definitions to use this from C code. The function sizes
30 * defines there must be kept in sync with this file!
31 */
32
33.macro ld32	reg
34	retl
35	 ld	[%o0], %f\reg
36.endm
37
38.macro st32	reg
39	retl
40	 st	%f\reg, [%o0]
41.endm
42
43.macro ld64	reg
44	retl
45	 ldd	[%o0], %f\reg
46.endm
47
48.macro st64	reg
49	retl
50	 std	%f\reg, [%o0]
51.endm
52
53/* The actual function arrays. */
54	.globl	__fpu_ld32
55__fpu_ld32:
56	ld32	0
57	ld32	1
58	ld32	2
59	ld32	3
60	ld32	4
61	ld32	5
62	ld32	6
63	ld32	7
64	ld32	8
65	ld32	9
66	ld32	10
67	ld32	11
68	ld32	12
69	ld32	13
70	ld32	14
71	ld32	15
72	ld32	16
73	ld32	17
74	ld32	18
75	ld32	19
76	ld32	20
77	ld32	21
78	ld32	22
79	ld32	23
80	ld32	24
81	ld32	25
82	ld32	26
83	ld32	27
84	ld32	28
85	ld32	29
86	ld32	30
87	ld32	31
88
89	.globl	__fpu_st32
90__fpu_st32:
91	st32	0
92	st32	1
93	st32	2
94	st32	3
95	st32	4
96	st32	5
97	st32	6
98	st32	7
99	st32	8
100	st32	9
101	st32	10
102	st32	11
103	st32	12
104	st32	13
105	st32	14
106	st32	15
107	st32	16
108	st32	17
109	st32	18
110	st32	19
111	st32	20
112	st32	21
113	st32	22
114	st32	23
115	st32	24
116	st32	25
117	st32	26
118	st32	27
119	st32	28
120	st32	29
121	st32	30
122	st32	31
123
124	.globl	__fpu_ld64
125__fpu_ld64:
126	ld64	0
127	ld64	2
128	ld64	4
129	ld64	6
130	ld64	8
131	ld64	10
132	ld64	12
133	ld64	14
134	ld64	16
135	ld64	18
136	ld64	20
137	ld64	22
138	ld64	24
139	ld64	26
140	ld64	28
141	ld64	30
142	ld64	32
143	ld64	34
144	ld64	36
145	ld64	38
146	ld64	40
147	ld64	42
148	ld64	44
149	ld64	46
150	ld64	48
151	ld64	50
152	ld64	52
153	ld64	54
154	ld64	56
155	ld64	58
156	ld64	60
157	ld64	62
158
159	.globl	__fpu_st64
160__fpu_st64:
161	st64	0
162	st64	2
163	st64	4
164	st64	6
165	st64	8
166	st64	10
167	st64	12
168	st64	14
169	st64	16
170	st64	18
171	st64	20
172	st64	22
173	st64	24
174	st64	26
175	st64	28
176	st64	30
177	st64	32
178	st64	34
179	st64	36
180	st64	38
181	st64	40
182	st64	42
183	st64	44
184	st64	46
185	st64	48
186	st64	50
187	st64	52
188	st64	54
189	st64	56
190	st64	58
191	st64	60
192	st64	62
193