1/*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c 326695 2017-12-08 15:57:29Z pfg $
20 */
21#include "opt_ah.h"
22
23#include "ah.h"
24#include "ah_internal.h"
25#include "ah_devid.h"
26#ifdef AH_DEBUG
27#include "ah_desc.h"			/* NB: for HAL_PHYERR* */
28#endif
29
30#include "ar5212/ar5212.h"
31#include "ar5212/ar5212reg.h"
32#include "ar5212/ar5212phy.h"
33
34#define	AR_NUM_GPIO	6		/* 6 GPIO pins */
35#define	AR_GPIOD_MASK	0x0000002F	/* GPIO data reg r/w mask */
36
37/*
38 * Configure GPIO Output lines
39 */
40HAL_BOOL
41ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
42{
43	HALASSERT(gpio < AR_NUM_GPIO);
44
45	/*
46	 * NB: AR_GPIOCR_CR_A(pin) is all 1's so there's no need
47	 *     to clear the field before or'ing in the new value.
48	 */
49	OS_REG_WRITE(ah, AR_GPIOCR,
50		  OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio));
51
52	return AH_TRUE;
53}
54
55/*
56 * Configure GPIO Input lines
57 */
58HAL_BOOL
59ar5212GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
60{
61	HALASSERT(gpio < AR_NUM_GPIO);
62
63	OS_REG_WRITE(ah, AR_GPIOCR,
64		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
65		| AR_GPIOCR_CR_N(gpio));
66
67	return AH_TRUE;
68}
69
70/*
71 * Once configured for I/O - set output lines
72 */
73HAL_BOOL
74ar5212GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
75{
76	uint32_t reg;
77
78	HALASSERT(gpio < AR_NUM_GPIO);
79
80	reg =  OS_REG_READ(ah, AR_GPIODO);
81	reg &= ~(1 << gpio);
82	reg |= (val&1) << gpio;
83
84	OS_REG_WRITE(ah, AR_GPIODO, reg);
85	return AH_TRUE;
86}
87
88/*
89 * Once configured for I/O - get input lines
90 */
91uint32_t
92ar5212GpioGet(struct ath_hal *ah, uint32_t gpio)
93{
94	if (gpio < AR_NUM_GPIO) {
95		uint32_t val = OS_REG_READ(ah, AR_GPIODI);
96		val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
97		return val;
98	} else  {
99		return 0xffffffff;
100	}
101}
102
103/*
104 * Set the GPIO Interrupt
105 */
106void
107ar5212GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
108{
109	uint32_t val;
110
111	/* XXX bounds check gpio */
112	val = OS_REG_READ(ah, AR_GPIOCR);
113	val &= ~(AR_GPIOCR_CR_A(gpio) |
114		 AR_GPIOCR_INT_MASK | AR_GPIOCR_INT_ENA | AR_GPIOCR_INT_SEL);
115	val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA;
116	if (ilevel)
117		val |= AR_GPIOCR_INT_SELH;	/* interrupt on pin high */
118	else
119		val |= AR_GPIOCR_INT_SELL;	/* interrupt on pin low */
120
121	/* Don't need to change anything for low level interrupt. */
122	OS_REG_WRITE(ah, AR_GPIOCR, val);
123
124	/* Change the interrupt mask. */
125	(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
126}
127