Searched refs:pipeline (Results 26 - 50 of 74) sorted by relevance

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/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_pipeline.c15 /** komeda_pipeline_add - Add a pipeline to &komeda_dev */
29 DRM_ERROR("Request pipeline size too small.\n");
119 DRM_ERROR("Unknown pipeline resource ID: %d.\n", id);
159 return komeda_pipeline_get_first_component(c->pipeline, avail_inputs);
208 c->pipeline = pipe;
275 struct komeda_pipeline *pipe = c->pipeline;
342 return slave ? slave->pipeline : NULL;
H A Dkomeda_plane.c23 struct komeda_pipeline *pipe = kplane->layer->base.pipeline;
197 /* for komeda, which is pipeline can be share between crtcs */
265 get_possible_crtcs(kms, c->pipeline),
311 komeda_set_crtc_plane_mask(kms, c->pipeline, plane);
H A Dkomeda_pipeline_state.c60 /* Assign pipeline for crtc */
73 DRM_DEBUG_ATOMIC("CRTC%d required pipeline%d is busy.\n",
78 /* pipeline only can be disabled when the it is free or unused */
80 DRM_DEBUG_ATOMIC("Disabling a busy pipeline:%d.\n", pipe->id);
104 WARN_ON(!drm_modeset_is_locked(&c->pipeline->obj.lock));
140 * The big boss (CRTC) is for pipeline assignment, since &komeda_component isn't
142 * pipeline, only pipeline can be shared between crtc, and pipeline as a whole
146 * component->pipeline t
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H A Dkomeda_wb_connector.c26 dflow->input.component = &wb_layer->base.pipeline->compiz->base;
H A Dkomeda_pipeline.h21 /* pipeline component IDs */
76 * component into the display pipeline.
82 /** @pipeline: the komeda pipeline this component belongs to */
83 struct komeda_pipeline *pipeline; member in struct:komeda_component
119 * pipeline.
385 * Represent a complete display pipeline and hold all functional components.
388 /** @obj: link pipeline as private obj of drm_atomic_state */
394 /** @id: pipeline id */
396 /** @avail_comps: available components mask of pipeline */
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/linux-master/sound/soc/sof/
H A Dipc3-topology.c355 * @index: ID of the pipeline the component belongs to
520 struct sof_ipc_pipe_new *pipeline; local
524 pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL);
525 if (!pipeline)
528 /* configure pipeline IPC message */
529 pipeline->hdr.size = sizeof(*pipeline);
530 pipeline->hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_PIPE_NEW;
531 pipeline
2240 struct sof_ipc_pipe_new *pipeline; local
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/linux-master/drivers/gpu/drm/sun4i/
H A Dsun4i_drv.c218 * Also, in a dual display pipeline setup, both frontends can feed
221 * in the pipeline. Fortunately, the pipelines are perfectly symmetric,
223 * from the frontend. The only exception is the third pipeline in
311 * The connectors will be the last nodes in our pipeline, we
382 struct device_node *pipeline = of_parse_phandle(np, local
385 if (!pipeline)
388 kfifo_put(&list.fifo, pipeline);
/linux-master/drivers/staging/media/ipu3/
H A Dipu3.h110 struct media_pipeline pipeline; member in struct:imgu_media_pipe
H A Dipu3-css-fw.c24 bi->info.isp.sp.id, bi->info.isp.sp.pipeline.mode,
194 if (bi->info.isp.sp.pipeline.mode >= IPU3_CSS_PIPE_ID_NUM)
/linux-master/drivers/gpu/drm/ci/
H A Dlava-submit.sh38 --pipeline-info "$CI_JOB_NAME: $CI_PIPELINE_URL on $CI_COMMIT_REF_NAME ${CI_NODE_INDEX}/${CI_NODE_TOTAL}" \
/linux-master/drivers/staging/media/atomisp/pci/
H A Dsh_css.c158 * pipeline,
479 if (pipe->pipeline.stages)
480 binary = pipe->pipeline.stages->binary;
929 if (pipe->pipeline.stages)
930 if (pipe->pipeline.stages->binary)
931 binary = pipe->pipeline.stages->binary;
1178 sh_css_sp_init_pipeline(&me->pipeline,
1197 stage = me->pipeline.stages;
1199 me->pipeline.current_stage = stage;
1578 * creates a host pipeline skeleto
3476 struct ia_css_pipeline *pipeline; local
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H A Dsh_css_params.c882 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); local
886 for (stage = pipeline->stages; stage; stage = stage->next) {
888 process(pipeline->pipe_id, stage, params);
3096 struct ia_css_pipeline *pipeline; local
3102 pipeline = ia_css_pipe_get_pipeline(pipe);
3116 cur_map = &params->pipe_ddr_ptrs[pipeline->pipe_id];
3117 cur_map_size = &params->pipe_ddr_ptrs_size[pipeline->pipe_id];
3125 /* we have to do this per pipeline because */
3128 pipeline->stages);
3142 for (stage = pipeline
4533 struct ia_css_pipeline *pipeline; local
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H A Dsh_css_sp.c110 sh_css_isp_stage.binary_info.pipeline.top_cropping;
776 static int configure_isp_from_args(const struct sh_css_sp_pipeline *pipeline, argument
790 ret = ia_css_qplane_configure(pipeline, binary, &binary->in_frame_info);
814 ret = ia_css_raw_configure(pipeline, binary, ia_css_frame_get_info(args->in_frame),
826 * without crashing, but the pipeline should likely be built without
829 ret = ia_css_ref_configure(binary, args->delay_frames, pipeline->dvs_frame_delay);
954 sh_css_sp_stage.isp_pipe_version = (uint8_t)info->pipeline.isp_pipe_version;
1023 if (binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_PREVIEW &&
1191 dev_err(atomisp_dev, "%s called on a pipeline without stages\n",
1221 /* Init pipeline dat
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/linux-master/arch/x86/platform/olpc/
H A Dxo1-wakeup.S35 # Control registers were modified, pipeline resync is needed
/linux-master/drivers/gpu/drm/xen/
H A Dxen_drm_front.c121 int xen_drm_front_mode_set(struct xen_drm_front_drm_pipeline *pipeline, argument
131 front_info = pipeline->drm_info->front_info;
132 evtchnl = &front_info->evt_pairs[pipeline->index].req;
379 xen_drm_front_kms_on_frame_done(&drm_info->pipeline[conn_idx],
/linux-master/drivers/isdn/mISDN/
H A Ddsp_core.c32 * - (7) pipeline
558 printk(KERN_DEBUG "%s: pipeline config string "
562 dsp->pipeline.inuse = 1;
564 ret = dsp_pipeline_build(&dsp->pipeline,
717 /* pipeline */
718 if (dsp->pipeline.inuse)
719 dsp_pipeline_process_rx(&dsp->pipeline, skb->data,
985 dsp_pipeline_destroy(&dsp->pipeline);
1098 /* init pipeline append to list */
1100 dsp_pipeline_init(&ndsp->pipeline);
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H A Ddsp_dtmf.c83 /* check if pipeline exists */
84 if (dsp->pipeline.inuse) {
87 "because pipeline exists.\n",
/linux-master/arch/sparc/lib/
H A DM7memset.S64 * instruction in the pipeline. That avoids various pipeline delays,
188 ! get store pipeline moving
223 ! to keep the store pipeline moving.
/linux-master/drivers/staging/media/deprecated/atmel/
H A Datmel-isc-base.c55 /* In here we set the v4l2 controls w.r.t. our pipeline config */
71 /* In here we set our actual hw pipeline config */
210 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) argument
220 val = pipeline & BIT(i) ? 1 : 0;
221 regmap_field_write(isc->pipeline[i], val);
224 if (!pipeline)
300 u32 pfe_cfg0, dcfg, mask, pipeline; local
304 pipeline = isc->config.bits_pipeline;
320 /* Set the pipeline */
321 isc_set_pipeline(isc, pipeline);
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H A Datmel-isc.h97 * struct fmt_config - ISC format configuration and internal pipeline
111 * @bits_pipeline: Configuration of the pipeline, which modules are enabled
225 * @pipeline: configuration of the ISC pipeline
252 * @adapt_pipeline: pointer to a function that adapts the pipeline bits
253 * to the product specific pipeline
297 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; member in struct:isc_device
/linux-master/drivers/media/platform/microchip/
H A Dmicrochip-isc-base.c46 /* In here we set the v4l2 controls w.r.t. our pipeline config */
62 /* In here we set our actual hw pipeline config */
200 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) argument
210 val = pipeline & BIT(i) ? 1 : 0;
211 regmap_field_write(isc->pipeline[i], val);
214 if (!pipeline)
290 u32 pfe_cfg0, dcfg, mask, pipeline; local
294 pipeline = isc->config.bits_pipeline;
310 /* Set the pipeline */
311 isc_set_pipeline(isc, pipeline);
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H A Dmicrochip-isc.h98 * struct fmt_config - ISC format configuration and internal pipeline
112 * @bits_pipeline: Configuration of the pipeline, which modules are enabled
236 * @pipeline: configuration of the ISC pipeline
263 * @adapt_pipeline: pointer to a function that adapts the pipeline bits
264 * to the product specific pipeline
275 * @mpipe: media device pipeline used by the isc
314 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; member in struct:isc_device
/linux-master/drivers/staging/media/atomisp/pci/runtime/ifmtr/src/
H A Difmtr.c113 binary->info->sp.pipeline.mode != IA_CSS_BINARY_MODE_COPY)
305 && binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY)) {
/linux-master/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_kms.h121 struct mdp5_pipeline pipeline; member in struct:mdp5_crtc_state
/linux-master/include/drm/ttm/
H A Dttm_bo.h423 bool pipeline,

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