/linux-master/drivers/thermal/st/ |
H A D | st_thermal_memmap.c | 123 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 124 if (IS_ERR(sensor->mmio_base)) 125 return PTR_ERR(sensor->mmio_base); 127 sensor->regmap = devm_regmap_init_mmio(dev, sensor->mmio_base,
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H A D | st_thermal.h | 92 void __iomem *mmio_base; member in struct:st_thermal_sensor
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/linux-master/drivers/video/fbdev/mb862xx/ |
H A D | mb862xxfbdrv.c | 624 par->host = par->mmio_base; 625 par->i2c = par->mmio_base + MB862XX_I2C_BASE; 626 par->disp = par->mmio_base + MB862XX_DISP_BASE; 627 par->cap = par->mmio_base + MB862XX_CAP_BASE; 628 par->draw = par->mmio_base + MB862XX_DRAW_BASE; 629 par->geo = par->mmio_base + MB862XX_GEO_BASE; 630 par->pio = par->mmio_base + MB862XX_PIO_BASE; 725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); 726 if (par->mmio_base == NULL) { 772 iounmap(par->mmio_base); [all...] |
/linux-master/drivers/platform/mellanox/ |
H A D | mlxbf-pmc.c | 109 * @mmio_base: The VA at which the PMC block is mapped 121 void __iomem *mmio_base; member in struct:mlxbf_pmc_block_info 1099 return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + 1118 pmcaddr = pmc->block[blk_num].mmio_base + 1123 pmcaddr = pmc->block[blk_num].mmio_base + 1175 addr = pmc->block[blk_num].mmio_base + 1197 addr = pmc->block[blk_num].mmio_base + 1234 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + 1248 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + 1259 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_reg_sr.c | 220 u32 mmio_base = hwe->mmio_base; local 244 xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), 251 u32 addr = RING_NOPID(mmio_base).addr; 253 xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
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H A D | xe_execlist.c | 80 xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base), 82 xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base)); 83 xe_mmio_write32(gt, RING_MODE(hwe->mmio_base), 86 xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base), 88 xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base), 90 xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base), 172 lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base)); 173 hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
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H A D | xe_hw_engine_types.h | 121 /** @mmio_base: MMIO base address of this hw engine*/ 122 u32 mmio_base; member in struct:xe_hw_engine 172 /** @mmio_base: MMIO base address of this hw engine*/ 173 u32 mmio_base; member in struct:xe_hw_engine_snapshot
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/linux-master/drivers/net/ethernet/broadcom/ |
H A D | bgmac.c | 46 if (!ring->mmio_base) 53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 68 ring->mmio_base, val); 71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 73 ring->mmio_base + BGMAC_DMA_TX_STATUS, 77 ring->mmio_base); 79 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 82 ring->mmio_base); 91 ctl = bgmac_read(bgmac, ring->mmio_base [all...] |
/linux-master/drivers/acpi/ |
H A D | acpi_lpss.c | 97 void __iomem *mmio_base; member in struct:lpss_private_data 135 val = readl(pdata->mmio_base + offset); 136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 138 val = readl(pdata->mmio_base + LPSS_UART_CPR); 141 val = readl(pdata->mmio_base + offset); 143 writel(val, pdata->mmio_base + offset); 153 val = readl(pdata->mmio_base + offset); 155 writel(val, pdata->mmio_base + offset); 194 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 197 writel(0, pdata->mmio_base [all...] |
/linux-master/drivers/net/wireless/broadcom/b43legacy/ |
H A D | dma.h | 145 u16 mmio_base; member in struct:b43legacy_dmaring 171 return b43legacy_read32(ring->dev, ring->mmio_base + offset); 178 b43legacy_write32(ring->dev, ring->mmio_base + offset, value);
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H A D | pio.c | 113 switch (queue->mmio_base) { 328 queue->mmio_base = pio_mmio_base; 340 qsize = b43legacy_read16(dev, queue->mmio_base 545 B43legacy_WARN_ON(queue->mmio_base != B43legacy_MMIO_PIO1_BASE); 585 if (unlikely(len == 0 && queue->mmio_base != 591 if (queue->mmio_base == B43legacy_MMIO_PIO4_BASE) 603 (queue->mmio_base == B43legacy_MMIO_PIO1_BASE), 607 if (queue->mmio_base == B43legacy_MMIO_PIO4_BASE) {
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/linux-master/drivers/video/fbdev/ |
H A D | asiliantfb.c | 49 #define mmio_base (p->screen_base + 0x400000) macro 52 writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \ 87 readb(mmio_base + 0x7b4); 218 writeb(0xc7, mmio_base + 0x784); /* set misc output reg */ 220 writeb(0x07, mmio_base + 0x784); /* set misc output reg */ 318 writeb(regno, mmio_base + 0x790); 320 writeb(red, mmio_base + 0x791); 321 writeb(green, mmio_base + 0x791); 322 writeb(blue, mmio_base [all...] |
H A D | pvr2fb.c | 82 #define DISP_BASE par->mmio_base 144 void __iomem *mmio_base; /* MMIO base */ member in struct:pvr2fb_par 234 fb_writel(type, par->mmio_base + 0x108); 241 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno)); 799 par->mmio_base = ioremap(pvr2_fix.mmio_start, 801 if (!par->mmio_base) { 838 rev = fb_readl(par->mmio_base + 0x04); 866 if (par->mmio_base) 867 iounmap(par->mmio_base); 933 if (currentpar->mmio_base) { [all...] |
/linux-master/drivers/thermal/intel/int340x_thermal/ |
H A D | processor_thermal_wt_hint.c | 69 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); 201 int_status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); 214 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);
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/linux-master/drivers/input/keyboard/ |
H A D | ep93xx_keypad.c | 71 void __iomem *mmio_base; member in struct:ep93xx_keypad 90 status = __raw_readl(keypad->mmio_base + KEY_REG); 154 __raw_writel(val, keypad->mmio_base + KEY_INIT); 253 keypad->mmio_base = devm_platform_ioremap_resource(pdev, 0); 254 if (IS_ERR(keypad->mmio_base)) 255 return PTR_ERR(keypad->mmio_base);
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_gmbus_regs.h | 11 #define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base)
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/linux-master/arch/powerpc/kernel/ |
H A D | udbg_16550.c | 159 unsigned char __iomem *mmio_base; member in union:__anon20 188 return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride)); 193 out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data); 201 udbg_uart.mmio_base = addr;
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/linux-master/drivers/gpu/drm/msm/disp/mdp5/ |
H A D | mdp5_ctl.h | 18 void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);
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/linux-master/include/linux/soundwire/ |
H A D | sdw_amd.h | 142 * @mmio_base: mmio base of SoundWire registers 153 void __iomem *mmio_base; member in struct:sdw_amd_res
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/linux-master/drivers/video/fbdev/aty/ |
H A D | radeonfb.h | 299 void __iomem *mmio_base; member in struct:radeonfb_info 376 #define INREG8(addr) readb((rinfo->mmio_base)+addr) 377 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 378 #define INREG16(addr) readw((rinfo->mmio_base)+addr) 379 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 380 #define INREG(addr) readl((rinfo->mmio_base)+addr) 381 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
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/linux-master/drivers/ata/ |
H A D | sata_svw.c | 416 void __iomem *mmio_base; local 461 mmio_base = host->iomap[bar_pos]; 470 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset); 484 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, 485 mmio_base + K2_SATA_SICR1_OFFSET); 488 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); 489 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
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H A D | sata_inic162x.c | 234 void __iomem *mmio_base; member in struct:inic_host_priv 268 return hpriv->mmio_base + ap->port_no * PORT_SIZE; 426 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); 752 static int init_controller(void __iomem *mmio_base, u16 hctl) argument 762 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); 763 readw(mmio_base + HOST_CTL); /* flush */ 767 val = readw(mmio_base + HOST_CTL); 777 void __iomem *port_base = mmio_base + i * PORT_SIZE; 784 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); 785 val = readw(mmio_base [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_engine.h | 59 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base)) 69 lower_reg__((engine__)->mmio_base), \ 70 upper_reg__((engine__)->mmio_base)) 73 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__))) 76 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
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/linux-master/sound/soc/pxa/ |
H A D | pxa-ssp.c | 126 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); 127 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); 128 priv->to = __raw_readl(ssp->mmio_base + SSTO); 129 priv->psp = __raw_readl(ssp->mmio_base + SSPSP); 144 __raw_writel(sssr, ssp->mmio_base + SSSR); 145 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); 146 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1); 147 __raw_writel(priv->to, ssp->mmio_base + SSTO); 148 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
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/linux-master/sound/soc/xilinx/ |
H A D | xlnx_formatter_pcm.c | 247 static int xlnx_formatter_pcm_reset(void __iomem *mmio_base) argument 251 val = readl(mmio_base + XLNX_AUD_CTRL); 253 writel(val, mmio_base + XLNX_AUD_CTRL); 255 val = readl(mmio_base + XLNX_AUD_CTRL); 260 val = readl(mmio_base + XLNX_AUD_CTRL); 268 static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream) argument 272 val = readl(mmio_base + XLNX_AUD_CTRL); 277 writel(val, mmio_base + XLNX_AUD_CTRL);
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