1251881Speter/* 2251881Speter * drivers/video/asiliantfb.c 3251881Speter * frame buffer driver for Asiliant 69000 chip 4251881Speter * Copyright (C) 2001-2003 Saito.K & Jeanne 5251881Speter * 6251881Speter * from driver/video/chipsfb.c and, 7251881Speter * 8251881Speter * drivers/video/asiliantfb.c -- frame buffer device for 9251881Speter * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies) 10251881Speter * Author: apc@agelectronics.co.uk 11251881Speter * Copyright (C) 2000 AG Electronics 12251881Speter * Note: the data sheets don't seem to be available from Asiliant. 13251881Speter * They are available by searching developer.intel.com, but are not otherwise 14251881Speter * linked to. 15251881Speter * 16251881Speter * This driver should be portable with minimal effort to the 69000 display 17251881Speter * chip, and to the twin-display mode of the 69030. 18251881Speter * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks) 19251881Speter * 20251881Speter * Derived from the CT65550 driver chipsfb.c: 21251881Speter * Copyright (C) 1998 Paul Mackerras 22251881Speter * ...which was derived from the Powermac "chips" driver: 23251881Speter * Copyright (C) 1997 Fabio Riccardi. 24251881Speter * And from the frame buffer device for Open Firmware-initialized devices: 25251881Speter * Copyright (C) 1997 Geert Uytterhoeven. 26251881Speter * 27251881Speter * This file is subject to the terms and conditions of the GNU General Public 28251881Speter * License. See the file COPYING in the main directory of this archive for 29251881Speter * more details. 30251881Speter */ 31251881Speter 32251881Speter#include <linux/aperture.h> 33251881Speter#include <linux/module.h> 34251881Speter#include <linux/kernel.h> 35251881Speter#include <linux/errno.h> 36251881Speter#include <linux/string.h> 37251881Speter#include <linux/mm.h> 38251881Speter#include <linux/vmalloc.h> 39251881Speter#include <linux/delay.h> 40251881Speter#include <linux/interrupt.h> 41251881Speter#include <linux/fb.h> 42251881Speter#include <linux/init.h> 43251881Speter#include <linux/pci.h> 44251881Speter#include <asm/io.h> 45251881Speter 46251881Speter/* Built in clock of the 69030 */ 47251881Speterstatic const unsigned Fref = 14318180; 48251881Speter 49322442Speter#define mmio_base (p->screen_base + 0x400000) 50251881Speter 51251881Speter#define mm_write_ind(num, val, ap, dp) do { \ 52251881Speter writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \ 53251881Speter} while (0) 54362181Sdim 55257936Speterstatic void mm_write_xr(struct fb_info *p, u8 reg, u8 data) 56251881Speter{ 57251881Speter mm_write_ind(reg, data, 0x7ac, 0x7ad); 58251881Speter} 59251881Speter#define write_xr(num, val) mm_write_xr(p, num, val) 60251881Speter 61251881Speterstatic void mm_write_fr(struct fb_info *p, u8 reg, u8 data) 62251881Speter{ 63251881Speter mm_write_ind(reg, data, 0x7a0, 0x7a1); 64251881Speter} 65251881Speter#define write_fr(num, val) mm_write_fr(p, num, val) 66251881Speter 67251881Speterstatic void mm_write_cr(struct fb_info *p, u8 reg, u8 data) 68251881Speter{ 69251881Speter mm_write_ind(reg, data, 0x7a8, 0x7a9); 70251881Speter} 71251881Speter#define write_cr(num, val) mm_write_cr(p, num, val) 72251881Speter 73251881Speterstatic void mm_write_gr(struct fb_info *p, u8 reg, u8 data) 74251881Speter{ 75251881Speter mm_write_ind(reg, data, 0x79c, 0x79d); 76251881Speter} 77251881Speter#define write_gr(num, val) mm_write_gr(p, num, val) 78251881Speter 79251881Speterstatic void mm_write_sr(struct fb_info *p, u8 reg, u8 data) 80251881Speter{ 81251881Speter mm_write_ind(reg, data, 0x788, 0x789); 82251881Speter} 83251881Speter#define write_sr(num, val) mm_write_sr(p, num, val) 84251881Speter 85251881Speterstatic void mm_write_ar(struct fb_info *p, u8 reg, u8 data) 86251881Speter{ 87251881Speter readb(mmio_base + 0x7b4); 88251881Speter mm_write_ind(reg, data, 0x780, 0x780); 89251881Speter} 90251881Speter#define write_ar(num, val) mm_write_ar(p, num, val) 91251881Speter 92251881Speterstatic int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *); 93251881Speterstatic int asiliantfb_check_var(struct fb_var_screeninfo *var, 94251881Speter struct fb_info *info); 95251881Speterstatic int asiliantfb_set_par(struct fb_info *info); 96251881Speterstatic int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 97251881Speter u_int transp, struct fb_info *info); 98251881Speter 99251881Speterstatic const struct fb_ops asiliantfb_ops = { 100251881Speter .owner = THIS_MODULE, 101251881Speter FB_DEFAULT_IOMEM_OPS, 102251881Speter .fb_check_var = asiliantfb_check_var, 103251881Speter .fb_set_par = asiliantfb_set_par, 104251881Speter .fb_setcolreg = asiliantfb_setcolreg, 105251881Speter}; 106251881Speter 107251881Speter/* Calculate the ratios for the dot clocks without using a single long long 108251881Speter * value */ 109251881Speterstatic void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div) 110251881Speter{ 111251881Speter unsigned pixclock = *ppixclock; 112251881Speter unsigned Ftarget; 113251881Speter unsigned n; 114251881Speter unsigned best_error = 0xffffffff; 115251881Speter unsigned best_m = 0xffffffff, 116251881Speter best_n = 0xffffffff; 117251881Speter unsigned ratio; 118251881Speter unsigned remainder; 119251881Speter unsigned char divisor = 0; 120251881Speter 121251881Speter /* Calculate the frequency required. This is hard enough. */ 122251881Speter ratio = 1000000 / pixclock; 123251881Speter remainder = 1000000 % pixclock; 124251881Speter Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock; 125251881Speter 126251881Speter while (Ftarget < 100000000) { 127251881Speter divisor += 0x10; 128251881Speter Ftarget <<= 1; 129251881Speter } 130251881Speter 131251881Speter ratio = Ftarget / Fref; 132251881Speter remainder = Ftarget % Fref; 133251881Speter 134251881Speter /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz, 135251881Speter * together with 3 <= n <= 257. */ 136251881Speter for (n = 3; n <= 257; n++) { 137251881Speter unsigned m = n * ratio + (n * remainder) / Fref; 138251881Speter 139251881Speter /* 3 <= m <= 257 */ 140251881Speter if (m >= 3 && m <= 257) { 141251881Speter unsigned new_error = Ftarget * n >= Fref * m ? 142251881Speter ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n)); 143251881Speter if (new_error < best_error) { 144251881Speter best_n = n; 145251881Speter best_m = m; 146251881Speter best_error = new_error; 147251881Speter } 148251881Speter } 149251881Speter /* But if VLD = 4, then 4m <= 1028 */ 150251881Speter else if (m <= 1028) { 151251881Speter /* remember there are still only 8-bits of precision in m, so 152251881Speter * avoid over-optimistic error calculations */ 153251881Speter unsigned new_error = Ftarget * n >= Fref * (m & ~3) ? 154251881Speter ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n)); 155251881Speter if (new_error < best_error) { 156251881Speter best_n = n; 157251881Speter best_m = m; 158251881Speter best_error = new_error; 159251881Speter } 160251881Speter } 161251881Speter } 162251881Speter if (best_m > 257) 163251881Speter best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */ 164251881Speter else 165251881Speter divisor |= 4; /* or set VCO loop divide to 1 */ 166251881Speter *dclk2_m = best_m - 2; 167251881Speter *dclk2_n = best_n - 2; 168251881Speter *dclk2_div = divisor; 169251881Speter *ppixclock = pixclock; 170251881Speter return; 171251881Speter} 172251881Speter 173251881Speterstatic void asiliant_set_timing(struct fb_info *p) 174251881Speter{ 175251881Speter unsigned hd = p->var.xres / 8; 176251881Speter unsigned hs = (p->var.xres + p->var.right_margin) / 8; 177251881Speter unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8; 178251881Speter unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8; 179251881Speter unsigned vd = p->var.yres; 180251881Speter unsigned vs = p->var.yres + p->var.lower_margin; 181251881Speter unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len; 182251881Speter unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len; 183251881Speter unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8; 184251881Speter 185251881Speter if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) { 186251881Speter write_fr(0x01, 0x02); /* LCD */ 187251881Speter } else { 188251881Speter write_fr(0x01, 0x01); /* CRT */ 189251881Speter } 190251881Speter 191251881Speter write_cr(0x11, (ve - 1) & 0x0f); 192362181Sdim write_cr(0x00, (ht - 5) & 0xff); 193251881Speter write_cr(0x01, hd - 1); 194251881Speter write_cr(0x02, hd); 195251881Speter write_cr(0x03, ((ht - 1) & 0x1f) | 0x80); 196251881Speter write_cr(0x04, hs); 197251881Speter write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f)); 198251881Speter write_cr(0x3c, (ht - 1) & 0xc0); 199251881Speter write_cr(0x06, (vt - 2) & 0xff); 200251881Speter write_cr(0x30, (vt - 2) >> 8); 201251881Speter write_cr(0x07, 0x00); 202251881Speter write_cr(0x08, 0x00); 203362181Sdim write_cr(0x09, 0x00); 204251881Speter write_cr(0x10, (vs - 1) & 0xff); 205251881Speter write_cr(0x32, ((vs - 1) >> 8) & 0xf); 206251881Speter write_cr(0x11, ((ve - 1) & 0x0f) | 0x80); 207251881Speter write_cr(0x12, (vd - 1) & 0xff); 208251881Speter write_cr(0x31, ((vd - 1) & 0xf00) >> 8); 209362181Sdim write_cr(0x13, wd & 0xff); 210362181Sdim write_cr(0x41, (wd & 0xf00) >> 8); 211251881Speter write_cr(0x15, (vs - 1) & 0xff); 212251881Speter write_cr(0x33, ((vs - 1) >> 8) & 0xf); 213251881Speter write_cr(0x38, ((ht - 5) & 0x100) >> 8); 214251881Speter write_cr(0x16, (vt - 1) & 0xff); 215251881Speter write_cr(0x18, 0x00); 216251881Speter 217362181Sdim if (p->var.xres == 640) { 218362181Sdim writeb(0xc7, mmio_base + 0x784); /* set misc output reg */ 219251881Speter } else { 220251881Speter writeb(0x07, mmio_base + 0x784); /* set misc output reg */ 221251881Speter } 222251881Speter} 223362181Sdim 224251881Speterstatic int asiliantfb_check_var(struct fb_var_screeninfo *var, 225251881Speter struct fb_info *p) 226251881Speter{ 227251881Speter unsigned long Ftarget, ratio, remainder; 228251881Speter 229251881Speter if (!var->pixclock) 230251881Speter return -EINVAL; 231251881Speter 232251881Speter ratio = 1000000 / var->pixclock; 233251881Speter remainder = 1000000 % var->pixclock; 234251881Speter Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock; 235251881Speter 236251881Speter /* First check the constraint that the maximum post-VCO divisor is 32, 237251881Speter * and the maximum Fvco is 220MHz */ 238251881Speter if (Ftarget > 220000000 || Ftarget < 3125000) { 239289180Speter printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n"); 240251881Speter return -ENXIO; 241251881Speter } 242251881Speter var->xres_virtual = var->xres; 243251881Speter var->yres_virtual = var->yres; 244251881Speter 245251881Speter if (var->bits_per_pixel == 24) { 246362181Sdim var->red.offset = 16; 247251881Speter var->green.offset = 8; 248251881Speter var->blue.offset = 0; 249251881Speter var->red.length = var->blue.length = var->green.length = 8; 250251881Speter } else if (var->bits_per_pixel == 16) { 251251881Speter switch (var->red.offset) { 252251881Speter case 11: 253251881Speter var->green.length = 6; 254251881Speter break; 255251881Speter case 10: 256251881Speter var->green.length = 5; 257251881Speter break; 258251881Speter default: 259251881Speter return -EINVAL; 260251881Speter } 261251881Speter var->green.offset = 5; 262251881Speter var->blue.offset = 0; 263251881Speter var->red.length = var->blue.length = 5; 264251881Speter } else if (var->bits_per_pixel == 8) { 265251881Speter var->red.offset = var->green.offset = var->blue.offset = 0; 266251881Speter var->red.length = var->green.length = var->blue.length = 8; 267251881Speter } 268251881Speter return 0; 269251881Speter} 270251881Speter 271251881Speterstatic int asiliantfb_set_par(struct fb_info *p) 272251881Speter{ 273251881Speter u8 dclk2_m; /* Holds m-2 value for register */ 274251881Speter u8 dclk2_n; /* Holds n-2 value for register */ 275251881Speter u8 dclk2_div; /* Holds divisor bitmask */ 276251881Speter 277251881Speter /* Set pixclock */ 278251881Speter asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div); 279251881Speter 280251881Speter /* Set color depth */ 281251881Speter if (p->var.bits_per_pixel == 24) { 282251881Speter write_xr(0x81, 0x16); /* 24 bit packed color mode */ 283251881Speter write_xr(0x82, 0x00); /* Disable palettes */ 284251881Speter write_xr(0x20, 0x20); /* 24 bit blitter mode */ 285251881Speter } else if (p->var.bits_per_pixel == 16) { 286251881Speter if (p->var.red.offset == 11) 287251881Speter write_xr(0x81, 0x15); /* 16 bit color mode */ 288251881Speter else 289251881Speter write_xr(0x81, 0x14); /* 15 bit color mode */ 290251881Speter write_xr(0x82, 0x00); /* Disable palettes */ 291251881Speter write_xr(0x20, 0x10); /* 16 bit blitter mode */ 292251881Speter } else if (p->var.bits_per_pixel == 8) { 293251881Speter write_xr(0x0a, 0x02); /* Linear */ 294251881Speter write_xr(0x81, 0x12); /* 8 bit color mode */ 295251881Speter write_xr(0x82, 0x00); /* Graphics gamma enable */ 296251881Speter write_xr(0x20, 0x00); /* 8 bit blitter mode */ 297251881Speter } 298251881Speter p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3); 299251881Speter p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 300251881Speter write_xr(0xc4, dclk2_m); 301251881Speter write_xr(0xc5, dclk2_n); 302251881Speter write_xr(0xc7, dclk2_div); 303251881Speter /* Set up the CR registers */ 304251881Speter asiliant_set_timing(p); 305251881Speter return 0; 306251881Speter} 307251881Speter 308251881Speterstatic int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 309251881Speter u_int transp, struct fb_info *p) 310251881Speter{ 311251881Speter if (regno > 255) 312251881Speter return 1; 313251881Speter red >>= 8; 314251881Speter green >>= 8; 315251881Speter blue >>= 8; 316251881Speter 317251881Speter /* Set hardware palete */ 318251881Speter writeb(regno, mmio_base + 0x790); 319251881Speter udelay(1); 320251881Speter writeb(red, mmio_base + 0x791); 321251881Speter writeb(green, mmio_base + 0x791); 322251881Speter writeb(blue, mmio_base + 0x791); 323251881Speter 324251881Speter if (regno < 16) { 325251881Speter switch(p->var.red.offset) { 326251881Speter case 10: /* RGB 555 */ 327251881Speter ((u32 *)(p->pseudo_palette))[regno] = 328251881Speter ((red & 0xf8) << 7) | 329251881Speter ((green & 0xf8) << 2) | 330251881Speter ((blue & 0xf8) >> 3); 331251881Speter break; 332251881Speter case 11: /* RGB 565 */ 333251881Speter ((u32 *)(p->pseudo_palette))[regno] = 334251881Speter ((red & 0xf8) << 8) | 335251881Speter ((green & 0xfc) << 3) | 336251881Speter ((blue & 0xf8) >> 3); 337251881Speter break; 338251881Speter case 16: /* RGB 888 */ 339251881Speter ((u32 *)(p->pseudo_palette))[regno] = 340251881Speter (red << 16) | 341251881Speter (green << 8) | 342251881Speter (blue); 343251881Speter break; 344251881Speter } 345251881Speter } 346251881Speter 347251881Speter return 0; 348251881Speter} 349251881Speter 350251881Speterstruct chips_init_reg { 351251881Speter unsigned char addr; 352251881Speter unsigned char data; 353251881Speter}; 354251881Speter 355251881Speterstatic struct chips_init_reg chips_init_sr[] = 356251881Speter{ 357251881Speter {0x00, 0x03}, /* Reset register */ 358251881Speter {0x01, 0x01}, /* Clocking mode */ 359251881Speter {0x02, 0x0f}, /* Plane mask */ 360251881Speter {0x04, 0x0e} /* Memory mode */ 361251881Speter}; 362251881Speter 363251881Speterstatic struct chips_init_reg chips_init_gr[] = 364251881Speter{ 365251881Speter {0x03, 0x00}, /* Data rotate */ 366251881Speter {0x05, 0x00}, /* Graphics mode */ 367251881Speter {0x06, 0x01}, /* Miscellaneous */ 368251881Speter {0x08, 0x00} /* Bit mask */ 369251881Speter}; 370251881Speter 371251881Speterstatic struct chips_init_reg chips_init_ar[] = 372251881Speter{ 373251881Speter {0x10, 0x01}, /* Mode control */ 374289180Speter {0x11, 0x00}, /* Overscan */ 375251881Speter {0x12, 0x0f}, /* Memory plane enable */ 376251881Speter {0x13, 0x00} /* Horizontal pixel panning */ 377289180Speter}; 378251881Speter 379251881Speterstatic struct chips_init_reg chips_init_cr[] = 380251881Speter{ 381251881Speter {0x0c, 0x00}, /* Start address high */ 382251881Speter {0x0d, 0x00}, /* Start address low */ 383289180Speter {0x40, 0x00}, /* Extended Start Address */ 384251881Speter {0x41, 0x00}, /* Extended Start Address */ 385251881Speter {0x14, 0x00}, /* Underline location */ 386251881Speter {0x17, 0xe3}, /* CRT mode control */ 387251881Speter {0x70, 0x00} /* Interlace control */ 388251881Speter}; 389251881Speter 390251881Speter 391251881Speterstatic struct chips_init_reg chips_init_fr[] = 392251881Speter{ 393251881Speter {0x01, 0x02}, 394251881Speter {0x03, 0x08}, 395251881Speter {0x08, 0xcc}, 396251881Speter {0x0a, 0x08}, 397251881Speter {0x18, 0x00}, 398251881Speter {0x1e, 0x80}, 399251881Speter {0x40, 0x83}, 400251881Speter {0x41, 0x00}, 401251881Speter {0x48, 0x13}, 402322442Speter {0x4d, 0x60}, 403251881Speter {0x4e, 0x0f}, 404251881Speter 405251881Speter {0x0b, 0x01}, 406251881Speter 407251881Speter {0x21, 0x51}, 408251881Speter {0x22, 0x1d}, 409251881Speter {0x23, 0x5f}, 410251881Speter {0x20, 0x4f}, 411251881Speter {0x34, 0x00}, 412251881Speter {0x24, 0x51}, 413251881Speter {0x25, 0x00}, 414251881Speter {0x27, 0x0b}, 415251881Speter {0x26, 0x00}, 416251881Speter {0x37, 0x80}, 417251881Speter {0x33, 0x0b}, 418251881Speter {0x35, 0x11}, 419251881Speter {0x36, 0x02}, 420251881Speter {0x31, 0xea}, 421251881Speter {0x32, 0x0c}, 422251881Speter {0x30, 0xdf}, 423251881Speter {0x10, 0x0c}, 424251881Speter {0x11, 0xe0}, 425251881Speter {0x12, 0x50}, 426251881Speter {0x13, 0x00}, 427251881Speter {0x16, 0x03}, 428251881Speter {0x17, 0xbd}, 429251881Speter {0x1a, 0x00}, 430251881Speter}; 431251881Speter 432251881Speter 433251881Speterstatic struct chips_init_reg chips_init_xr[] = 434251881Speter{ 435251881Speter {0xce, 0x00}, /* set default memory clock */ 436251881Speter {0xcc, 200 }, /* MCLK ratio M */ 437289180Speter {0xcd, 18 }, /* MCLK ratio N */ 438251881Speter {0xce, 0x90}, /* MCLK divisor = 2 */ 439251881Speter 440251881Speter {0xc4, 209 }, 441289180Speter {0xc5, 118 }, 442289180Speter {0xc7, 32 }, 443289180Speter {0xcf, 0x06}, 444289180Speter {0x09, 0x01}, /* IO Control - CRT controller extensions */ 445289180Speter {0x0a, 0x02}, /* Frame buffer mapping */ 446289180Speter {0x0b, 0x01}, /* PCI burst write */ 447322442Speter {0x40, 0x03}, /* Memory access control */ 448289180Speter {0x80, 0x82}, /* Pixel pipeline configuration 0 */ 449289180Speter {0x81, 0x12}, /* Pixel pipeline configuration 1 */ 450289180Speter {0x82, 0x08}, /* Pixel pipeline configuration 2 */ 451289180Speter 452289180Speter {0xd0, 0x0f}, 453251881Speter {0xd1, 0x01}, 454251881Speter}; 455251881Speter 456251881Speterstatic void chips_hw_init(struct fb_info *p) 457251881Speter{ 458251881Speter int i; 459251881Speter 460251881Speter for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i) 461251881Speter write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); 462251881Speter write_xr(0x81, 0x12); 463251881Speter write_xr(0x82, 0x08); 464251881Speter write_xr(0x20, 0x00); 465289180Speter for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i) 466251881Speter write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); 467251881Speter for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i) 468251881Speter write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); 469251881Speter for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i) 470251881Speter write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); 471251881Speter /* Enable video output in attribute index register */ 472289180Speter writeb(0x20, mmio_base + 0x780); 473289180Speter for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i) 474289180Speter write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); 475362181Sdim for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i) 476251881Speter write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); 477362181Sdim} 478251881Speter 479251881Speterstatic const struct fb_fix_screeninfo asiliantfb_fix = { 480251881Speter .id = "Asiliant 69000", 481251881Speter .type = FB_TYPE_PACKED_PIXELS, 482251881Speter .visual = FB_VISUAL_PSEUDOCOLOR, 483251881Speter .accel = FB_ACCEL_NONE, 484251881Speter .line_length = 640, 485251881Speter .smem_len = 0x200000, /* 2MB */ 486251881Speter}; 487251881Speter 488251881Speterstatic const struct fb_var_screeninfo asiliantfb_var = { 489251881Speter .xres = 640, 490251881Speter .yres = 480, 491251881Speter .xres_virtual = 640, 492251881Speter .yres_virtual = 480, 493251881Speter .bits_per_pixel = 8, 494251881Speter .red = { .length = 8 }, 495251881Speter .green = { .length = 8 }, 496251881Speter .blue = { .length = 8 }, 497251881Speter .height = -1, 498251881Speter .width = -1, 499251881Speter .vmode = FB_VMODE_NONINTERLACED, 500251881Speter .pixclock = 39722, 501251881Speter .left_margin = 48, 502251881Speter .right_margin = 16, 503251881Speter .upper_margin = 33, 504251881Speter .lower_margin = 10, 505251881Speter .hsync_len = 96, 506251881Speter .vsync_len = 2, 507251881Speter}; 508251881Speter 509251881Speterstatic int init_asiliant(struct fb_info *p, unsigned long addr) 510251881Speter{ 511251881Speter int err; 512251881Speter 513251881Speter p->fix = asiliantfb_fix; 514251881Speter p->fix.smem_start = addr; 515251881Speter p->var = asiliantfb_var; 516251881Speter p->fbops = &asiliantfb_ops; 517251881Speter 518251881Speter err = fb_alloc_cmap(&p->cmap, 256, 0); 519251881Speter if (err) { 520251881Speter printk(KERN_ERR "C&T 69000 fb failed to alloc cmap memory\n"); 521251881Speter return err; 522251881Speter } 523251881Speter 524251881Speter err = register_framebuffer(p); 525251881Speter if (err < 0) { 526251881Speter printk(KERN_ERR "C&T 69000 framebuffer failed to register\n"); 527251881Speter fb_dealloc_cmap(&p->cmap); 528251881Speter return err; 529251881Speter } 530251881Speter 531251881Speter fb_info(p, "Asiliant 69000 frame buffer (%dK RAM detected)\n", 532251881Speter p->fix.smem_len / 1024); 533251881Speter 534251881Speter writeb(0xff, mmio_base + 0x78c); 535251881Speter chips_hw_init(p); 536251881Speter return 0; 537251881Speter} 538251881Speter 539251881Speterstatic int asiliantfb_pci_init(struct pci_dev *dp, 540251881Speter const struct pci_device_id *ent) 541251881Speter{ 542251881Speter unsigned long addr, size; 543251881Speter struct fb_info *p; 544251881Speter int err; 545251881Speter 546362181Sdim err = aperture_remove_conflicting_pci_devices(dp, "asiliantfb"); 547289180Speter if (err) 548289180Speter return err; 549289180Speter 550289180Speter if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) 551251881Speter return -ENODEV; 552362181Sdim addr = pci_resource_start(dp, 0); 553251881Speter size = pci_resource_len(dp, 0); 554251881Speter if (addr == 0) 555251881Speter return -ENODEV; 556251881Speter if (!request_mem_region(addr, size, "asiliantfb")) 557251881Speter return -EBUSY; 558251881Speter 559251881Speter p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev); 560251881Speter if (!p) { 561251881Speter release_mem_region(addr, size); 562251881Speter return -ENOMEM; 563251881Speter } 564251881Speter p->pseudo_palette = p->par; 565251881Speter p->par = NULL; 566251881Speter 567251881Speter p->screen_base = ioremap(addr, 0x800000); 568251881Speter if (p->screen_base == NULL) { 569251881Speter release_mem_region(addr, size); 570251881Speter framebuffer_release(p); 571251881Speter return -ENOMEM; 572251881Speter } 573251881Speter 574251881Speter pci_write_config_dword(dp, 4, 0x02800083); 575251881Speter writeb(3, p->screen_base + 0x400784); 576251881Speter 577251881Speter err = init_asiliant(p, addr); 578251881Speter if (err) { 579251881Speter iounmap(p->screen_base); 580289180Speter release_mem_region(addr, size); 581289180Speter framebuffer_release(p); 582289180Speter return err; 583289180Speter } 584289180Speter 585289180Speter pci_set_drvdata(dp, p); 586289180Speter return 0; 587289180Speter} 588289180Speter 589289180Speterstatic void asiliantfb_remove(struct pci_dev *dp) 590289180Speter{ 591289180Speter struct fb_info *p = pci_get_drvdata(dp); 592289180Speter 593289180Speter unregister_framebuffer(p); 594289180Speter fb_dealloc_cmap(&p->cmap); 595289180Speter iounmap(p->screen_base); 596289180Speter release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0)); 597289180Speter framebuffer_release(p); 598289180Speter} 599289180Speter 600289180Speterstatic const struct pci_device_id asiliantfb_pci_tbl[] = { 601289180Speter { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID }, 602289180Speter { 0 } 603289180Speter}; 604289180Speter 605289180SpeterMODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl); 606289180Speter 607251881Speterstatic struct pci_driver asiliantfb_driver = { 608251881Speter .name = "asiliantfb", 609289180Speter .id_table = asiliantfb_pci_tbl, 610289180Speter .probe = asiliantfb_pci_init, 611289180Speter .remove = asiliantfb_remove, 612289180Speter}; 613251881Speter 614251881Speterstatic int __init asiliantfb_init(void) 615251881Speter{ 616251881Speter if (fb_modesetting_disabled("asiliantfb")) 617289180Speter return -ENODEV; 618251881Speter 619289180Speter if (fb_get_options("asiliantfb", NULL)) 620251881Speter return -ENODEV; 621251881Speter 622289180Speter return pci_register_driver(&asiliantfb_driver); 623289180Speter} 624289180Speter 625251881Spetermodule_init(asiliantfb_init); 626251881Speter 627251881Speterstatic void __exit asiliantfb_exit(void) 628251881Speter{ 629251881Speter pci_unregister_driver(&asiliantfb_driver); 630362181Sdim} 631251881Speter 632289180SpeterMODULE_LICENSE("GPL"); 633362181Sdim