Searched refs:lanes (Results 26 - 50 of 277) sorted by relevance

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/linux-master/drivers/gpu/drm/tegra/
H A Ddp.h113 * @max_lanes: maximum number of lanes supported on the link
118 * @lanes: currently configured number of lanes
141 unsigned int lanes; member in struct:drm_dp_link
H A Ddsi.c40 unsigned int lanes; member in struct:tegra_dsi_state
71 unsigned int lanes; member in struct:tegra_dsi
471 return dsi->master->lanes + dsi->lanes;
474 return dsi->lanes + dsi->slave->lanes;
476 return dsi->lanes;
509 DSI_CONTROL_LANES(dsi->lanes - 1) |
593 unsigned int lanes = state->lanes; local
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/linux-master/net/ethtool/
H A Dcommon.h19 u8 lanes; member in struct:link_mode_info
H A Dfec.c76 if (stats->lanes[0] == ETHTOOL_STAT_NOT_SET) {
85 if (stats->lanes[i] == ETHTOOL_STAT_NOT_SET)
88 grp->stats[0] += stats->lanes[i];
89 grp->stats[grp->cnt++] = stats->lanes[i];
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dmcp89.c31 .lanes = { 3, 2, 1, 0 },
H A Dgm107.c57 .lanes = { 0, 1, 2, 3 },
/linux-master/drivers/pci/controller/
H A Dpcie-rockchip.c59 rockchip->lanes = 1;
60 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
61 if (!err && (rockchip->lanes == 0 ||
62 rockchip->lanes == 3 ||
63 rockchip->lanes > 4)) {
64 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
65 rockchip->lanes = 1;
248 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
362 /* inactive lanes ar
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/linux-master/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-lvds-phy.c207 if (mst_cfg->lanes != slv_cfg->lanes) {
208 dev_err(dev, "lanes mismatch(mst: %u vs slv: %u)\n",
209 mst_cfg->lanes, slv_cfg->lanes);
241 if (cfg->lanes != 4 && cfg->lanes != 3) {
242 dev_err(&phy->dev, "invalid data lanes(%u)\n", cfg->lanes);
/linux-master/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c91 u32 lanes; member in struct:dw_dsi
333 u32 lanes)
340 val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8);
366 u32 lanes)
373 dsi_set_phy_timer(base, phy, lanes);
397 for (i = 0; i < lanes; i++) {
550 dphy_req_kHz = mode->clock * bpp / dsi->lanes;
557 dsi_set_mipi_phy(base, phy, dsi->lanes);
568 DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n",
569 dsi->lanes, mod
331 dsi_set_phy_timer(void __iomem *base, struct mipi_phy_params *phy, u32 lanes) argument
364 dsi_set_mipi_phy(void __iomem *base, struct mipi_phy_params *phy, u32 lanes) argument
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/linux-master/drivers/staging/media/atomisp/pci/
H A Datomisp_csi2_bridge.c78 int lanes; member in struct:atomisp_sensor_config
86 .lanes = _LANES, \
539 int lanes = 1; local
546 lanes = cfg->lanes;
569 sensor->lanes = gmin_cfg_get_int(adev, "CsiLanes", lanes);
570 if (sensor->lanes > IPU_MAX_LANES) {
572 dev_name(&adev->dev), sensor->lanes);
/linux-master/drivers/gpu/drm/bridge/
H A Dnwl-dsi.c105 /* dsi lanes */
106 u32 lanes; member in struct:nwl_dsi
193 dsi->lanes * 8ULL * NSEC_PER_SEC);
217 if (dsi->lanes < 1 || dsi->lanes > 4)
220 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
221 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
352 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
355 if (device->lanes <
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/linux-master/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c242 unsigned long mode_flags, u32 lanes, u32 format,
254 pll_out_khz = mode->clock * bpp / lanes;
330 unsigned long mode_flags, u32 lanes, u32 format)
341 pll_out_khz = mode->clock * bpp / lanes;
373 px_clock_hz = DIV_ROUND_CLOSEST_ULL(1000ULL * pll_out_khz * lanes, bpp);
414 lanes * BITS_PER_BYTE, bpp);
241 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format, unsigned int *lane_mbps) argument
328 dw_mipi_dsi_stm_mode_valid(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format) argument
/linux-master/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-csi.c66 unsigned int lanes = sensor->lanes; local
69 if (lanes < 1 || lanes > 4)
72 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
170 sensor->lanes, cfg);
/linux-master/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c254 u32 lanes; member in struct:dw_mipi_dsi
324 if (device->lanes > dsi->plat_data->max_data_lanes) {
325 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
326 device->lanes);
330 dsi->lanes = device->lanes;
766 return minimum_lbccs[dsi->lanes - 1];
788 lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8);
890 N_LANES(dsi->lanes));
961 /* this instance is the slave, so add the master's lanes */
979 u32 lanes = dw_mipi_dsi_get_lanes(dsi); local
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/linux-master/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-csi2.c120 unsigned short lanes; member in struct:rzg2l_csi2
263 do_div(mbps, csi2->lanes * 1000000);
370 /* Select data lanes */
371 rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes));
650 csi2->lanes = vep->bus.mipi_csi2.num_data_lanes;
705 int lanes; local
708 if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) {
709 dev_err(csi2->dev, "Unsupported number of data-lanes
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/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_dsi.c573 u32 lanes; member in struct:vc4_dsi
732 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
733 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
734 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
737 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
738 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
739 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
742 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
743 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
744 (dsi->lanes >
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/linux-master/drivers/phy/allwinner/
H A Dphy-sun6i-mipi-dphy.c227 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
334 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
387 SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
473 if (dphy->config.lanes >= 1)
475 if (dphy->config.lanes >= 2)
477 if (dphy->config.lanes >= 3)
479 if (dphy->config.lanes == 4)
485 SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
/linux-master/drivers/staging/media/atomisp/include/linux/
H A Datomisp_platform.h128 unsigned int lanes; member in struct:intel_v4l2_subdev_table
212 int atomisp_register_sensor_no_gmin(struct v4l2_subdev *subdev, u32 lanes,
/linux-master/drivers/gpu/drm/exynos/
H A Dexynos_drm_dsi.c50 dsim->lanes = device->lanes;
/linux-master/include/media/
H A Dipu-bridge.h76 u8 lanes; member in struct:ipu_sensor_ssdb
136 u8 lanes; member in struct:ipu_sensor
/linux-master/drivers/media/i2c/
H A Dccs-pll.h22 /* op pix clock is for all lanes in total normally */
76 * @op_lanes: Number of operational lanes (input)
77 * @vt_lanes: Number of video timing lanes (input)
79 * @csi2.lanes: The number of the CSI-2 data lanes (input)
104 u8 lanes; member in struct:ccs_pll::__anon982
/linux-master/arch/arm/mach-omap2/
H A Ddisplay.c73 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) argument
103 reg |= (lanes << enable_shift) & enable_mask;
104 reg |= (lanes << pipd_shift) & pipd_mask;
/linux-master/drivers/gpu/drm/bridge/adv7511/
H A Dadv7533.c32 static const u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */
43 clock_div_by_lanes[dsi->lanes - 2] << 3);
73 /* set number of dsi lanes */
74 regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4);
157 dsi->lanes = adv->num_dsi_lanes;
173 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes);
/linux-master/drivers/staging/media/tegra-video/
H A Dcsi.c460 unsigned int port_num, unsigned int lanes,
473 * Each CSI brick has maximum of 4 lanes.
474 * For lanes more than 4, use multiple of immediate CSI bricks as gang.
476 if (lanes <= CSI_LANES_PER_BRICK) {
477 chan->numlanes = lanes;
481 chan->numgangports = lanes / CSI_LANES_PER_BRICK;
535 unsigned int lanes, portno, num_pads; local
567 lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes;
569 * Each CSI brick has maximum 4 data lanes.
570 * For lanes mor
458 tegra_csi_channel_alloc(struct tegra_csi *csi, struct device_node *node, unsigned int port_num, unsigned int lanes, unsigned int num_pads) argument
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/linux-master/drivers/gpu/drm/gma500/
H A Dintel_bios.c90 switch (edp_link_params->lanes) {
92 dev_priv->edp.lanes = 1;
95 dev_priv->edp.lanes = 2;
99 dev_priv->edp.lanes = 4;
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp);

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