/linux-master/tools/objtool/arch/powerpc/ |
H A D | decode.c | 44 struct instruction *insn) 78 unsigned long arch_jump_destination(struct instruction *insn)
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/linux-master/tools/objtool/include/objtool/ |
H A D | warn.h | 58 struct instruction *_insn = (insn); \ 69 struct instruction *_insn = (insn); \
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/linux-master/arch/arm/probes/kprobes/ |
H A D | test-core.h | 92 * After this, the instruction to be tested is defined with TEST_INSTRUCTION. 155 #define TEST_INSTRUCTION(instruction) \ 157 "1: "instruction" \n\t" \ 160 #define TEST_BRANCH_F(instruction) \ 161 TEST_INSTRUCTION(instruction) \ 165 #define TEST_BRANCH_B(instruction) \ 170 TEST_INSTRUCTION(instruction) 172 #define TEST_BRANCH_FX(instruction, codex) \ 173 TEST_INSTRUCTION(instruction) \ 179 #define TEST_BRANCH_BX(instruction, code [all...] |
/linux-master/tools/objtool/arch/loongarch/ |
H A D | decode.c | 18 unsigned long arch_jump_destination(struct instruction *insn) 79 struct instruction *insn) 100 struct instruction *insn) 118 struct instruction *insn, 177 struct instruction *insn, 221 struct instruction *insn) 238 * just treat it as a call instruction. 277 struct instruction *insn)
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/linux-master/drivers/crypto/intel/keembay/ |
H A D | ocs-aes.c | 527 enum ocs_instruction instruction) 554 val = (cipher << 14) | (mode << 8) | (instruction << 6) | 562 enum ocs_instruction instruction) 571 set_ocs_aes_command(aes_dev, cipher, mode, instruction); 605 enum ocs_instruction instruction, 608 /* Ensure cipher, mode and instruction are valid. */ 617 if (instruction != OCS_ENCRYPT && instruction != OCS_DECRYPT && 618 instruction != OCS_EXPAND && instruction ! 524 set_ocs_aes_command(struct ocs_aes_dev *aes_dev, enum ocs_cipher cipher, enum ocs_mode mode, enum ocs_instruction instruction) argument 559 ocs_aes_init(struct ocs_aes_dev *aes_dev, enum ocs_mode mode, enum ocs_cipher cipher, enum ocs_instruction instruction) argument 600 ocs_aes_validate_inputs(dma_addr_t src_dma_list, u32 src_size, const u8 *iv, u32 iv_size, dma_addr_t aad_dma_list, u32 aad_size, const u8 *tag, u32 tag_size, enum ocs_cipher cipher, enum ocs_mode mode, enum ocs_instruction instruction, dma_addr_t dst_dma_list) argument 796 ocs_aes_op(struct ocs_aes_dev *aes_dev, enum ocs_mode mode, enum ocs_cipher cipher, enum ocs_instruction instruction, dma_addr_t dst_dma_list, dma_addr_t src_dma_list, u32 src_size, u8 *iv, u32 iv_size) argument 925 ocs_aes_gcm_op(struct ocs_aes_dev *aes_dev, enum ocs_cipher cipher, enum ocs_instruction instruction, dma_addr_t dst_dma_list, dma_addr_t src_dma_list, u32 src_size, const u8 *iv, dma_addr_t aad_dma_list, u32 aad_size, u8 *out_tag, u32 tag_size) argument 1307 ocs_aes_ccm_op(struct ocs_aes_dev *aes_dev, enum ocs_cipher cipher, enum ocs_instruction instruction, dma_addr_t dst_dma_list, dma_addr_t src_dma_list, u32 src_size, u8 *iv, dma_addr_t adata_dma_list, u32 adata_size, u8 *in_tag, u32 tag_size) argument [all...] |
H A D | keembay-ocs-aes-core.c | 61 * @instruction: Instruction to be executed (encrypt / decrypt). 83 enum ocs_instruction instruction; member in struct:ocs_aes_rctx 310 enum ocs_instruction instruction, 328 if (instruction == OCS_ENCRYPT) 358 rctx->instruction = instruction; 413 if (rctx->mode == OCS_MODE_CBC && rctx->instruction == OCS_DECRYPT) 418 if (rctx->cts_swap && rctx->instruction == OCS_DECRYPT) 489 if (!(rctx->cts_swap && rctx->instruction == OCS_DECRYPT)) 549 rc = ocs_aes_op(aes_dev, rctx->mode, tctx->cipher, rctx->instruction, 308 kmb_ocs_sk_common(struct skcipher_request *req, enum ocs_cipher cipher, enum ocs_instruction instruction, enum ocs_mode mode) argument 594 kmb_ocs_aead_validate_input(struct aead_request *req, enum ocs_instruction instruction, enum ocs_mode mode) argument 635 kmb_ocs_aead_common(struct aead_request *req, enum ocs_cipher cipher, enum ocs_instruction instruction, enum ocs_mode mode) argument [all...] |
/linux-master/arch/m68k/ifpsp060/src/ |
H A D | isp.S | 337 # _imem_read_{word,long}() - read instruction word/longword # 366 # This handler fetches the first instruction longword from # 426 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 427 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr 549 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 550 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr 599 # The instruction that was just emulated was also being traced. The trace 600 # trap for this instruction will be lost unless we jump to the trace handler. 648 # the chk2 instruction should take a chk trap. so, here we must create a 649 # chk stack frame from an unimplemented integer instruction exceptio [all...] |
H A D | pfpsp.S | 548 set fmovm_flg, 0x40 # flag bit: fmovm instruction 585 # _imem_read_long() - read instruction longword # 591 # fout() - emulate an opclass 3 instruction # 612 # instruction, the 060 will take an overflow exception whether the # 614 # This handler emulates the instruction to determine what the correct # 621 # the default result (only if the instruction is opclass 3). For # 629 # Also, in the case of an opclass three instruction where # 648 # the FPIAR holds the "current PC" of the faulting instruction 650 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 651 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction pt [all...] |
/linux-master/drivers/scsi/aic7xxx/aicasm/ |
H A D | aicasm_insformat.h | 167 struct instruction { struct 171 STAILQ_ENTRY(instruction) links;
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H A D | aicasm.c | 100 static STAILQ_HEAD(,instruction) seq_program; 322 struct instruction *cur_instr; 351 struct instruction *cur_instr; 523 struct instruction *cur_instr; 603 /* Don't count this instruction as it is in a patch 731 struct instruction * 734 struct instruction *new_instr; 736 new_instr = (struct instruction *)malloc(sizeof(struct instruction)); 738 stop("Unable to malloc instruction objec [all...] |
/linux-master/net/nfc/hci/ |
H A D | hci.h | 17 u8 header; /* type -cmd,evt,rsp- + instruction */ 71 u8 type, u8 instruction, 77 u8 instruction, struct sk_buff *skb);
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/linux-master/arch/powerpc/xmon/ |
H A D | ppc.h | 128 /* Opcode is an e500 SPE floating point instruction. */ 217 /* A macro to extract the major opcode from an instruction. */ 220 /* A macro to determine if the instruction is a 2-byte VLE insn. */ 223 /* A macro to extract the major opcode from a VLE instruction. */ 246 operand value into an instruction, check this field. 253 (i is the instruction which we are filling in, o is a pointer to 257 instruction and the operand value. It will return the new value 258 of the instruction. If the ERRMSG argument is not NULL, then if 264 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); 267 extract this operand type from an instruction, chec [all...] |
/linux-master/arch/arm/mm/ |
H A D | abort-ev6.S | 14 * Purpose : obtain information about current aborted instruction. 25 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. 36 ldr r3, [r4] @ read aborted ARM instruction
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H A D | abort-lv4t.S | 13 * Purpose : obtain information about current aborted instruction. 29 ldr r8, [r4] @ read arm instruction 77 and r9, r8, #15 << 16 @ Extract 'n' from instruction 97 and r9, r8, #15 << 16 @ Extract 'n' from instruction 113 and r9, r8, #15 << 16 @ Extract 'n' from instruction 126 and r7, r8, #15 @ Extract 'm' from instruction 169 ldrh r8, [r4] @ read instruction
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/linux-master/arch/sh/kernel/ |
H A D | io_trapped.c | 273 insn_size_t instruction; local 283 if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc), 284 sizeof(instruction))) { 288 tmp = handle_unaligned_access(instruction, regs,
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/linux-master/arch/arm/include/asm/ |
H A D | traps.h | 39 asmlinkage void dump_backtrace_stm(u32 *stack, u32 instruction, const char *loglvl);
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/linux-master/arch/m68k/fpsp040/ |
H A D | bugfix.S | 65 | /* If the xu instruction is exceptional, we punt. 114 | /* If the xu instruction is exceptional, we punt. 247 | dest and the dest of the xu. We must clear the instruction in 248 | the cu and restore the state, allowing the instruction in the 249 | xu to complete. Remember, the instruction in the nu 251 | If the result of the xu instruction is not exceptional, we can 252 | restore the instruction from the cu to the frame and continue 275 | Check if the instruction which just completed was exceptional. 280 | It is necessary to isolate the result of the instruction in the 369 | dest and the dest of the xu. We must clear the instruction i [all...] |
H A D | x_ovfl.S | 14 | If the instruction is move_out, then garbage is stored in the 15 | destination. If the instruction is not move_out, then the 174 | CCs are defined to be 'not affected' for the opclass3 instruction.
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H A D | x_unimp.S | 4 | fpsp_unimp --- FPSP handler for unimplemented instruction 19 | instruction.
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H A D | x_fline.S | 8 | Next, determine if the instruction is an fmovecr with a non-zero 50 moveal EXC_PC+4(%a6),%a0 |get address of fline instruction 65 | ;if an FMOVECR instruction, fix stack
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/linux-master/arch/m68k/ifpsp060/ |
H A D | fskeleton.S | 111 | instruction. 130 | instruction. 149 | instruction. 168 | instruction. 189 | bit in the FPSR, and does an "rte". The instruction that caused the 227 | frame to the PC of the instruction causing the exception, and does an "rte". 228 | The execution of the instruction then proceeds with an enabled floating-point 245 | This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
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/linux-master/arch/arm/kernel/ |
H A D | phys2virt.S | 88 @ offset into the immediate field of the MOV instruction, or patch it 89 @ to a MVN instruction if the offset is negative. In this case, we 103 moveq r0, #0x200000 @ set bit 21, mov to mvn instruction 169 @ In the LPAE case, we use a MOVW instruction to carry the low offset 171 @ field of the subsequent MOV instruction, or patch it to a MVN 172 @ instruction if the offset is negative. We can distinguish MOVW 182 moveq r0, #0x400000 @ set bit 22, mov to mvn instruction 194 bfc ip, #0, #12 @ clear imm12 field of MOV[W] instruction
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H A D | swp_emulate.c | 12 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>] 64 * Macros/defines for extracting register numbers from instruction. 66 #define EXTRACT_REG_NUM(instruction, offset) \ 67 (((instruction) & (0xf << (offset))) >> (offset)) 72 * Bit 22 of the instruction encoding distinguishes between 124 pr_debug("SWP instruction on unaligned pointer!\n"); 156 * swp_handler logs the id of calling process, dissects the instruction, sanity 172 /* Condition failed - return to next instruction */ 183 pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n", 211 * instruction followin [all...] |
/linux-master/drivers/acpi/apei/ |
H A D | apei-base.c | 156 * "ip" is the instruction pointer of current instruction, 157 * "ctx->ip" specifies the next instruction to executed, 158 * instruction "run" function may change the "ctx->ip" to 168 if (entry->instruction >= ctx->instructions || 169 !ctx->ins_table[entry->instruction].run) { 171 "Invalid action table, unknown instruction type: %d\n", 172 entry->instruction); 175 run = ctx->ins_table[entry->instruction].run; 207 ins = entry->instruction; [all...] |
/linux-master/arch/arm/lib/ |
H A D | backtrace-clang.S | 39 * If the call instruction was a bl we can look at the callers branch 40 * instruction to calculate the saved pc. We can recover the pc in most cases, 82 * show_stack. It points at the instruction directly after the bl dump_stack. 133 * the instruction used to call the current function. 136 * called using a bl instruction. If the function start can be recovered sv_pc 147 1004: ldr r0, [sv_lr, #-4] @ get call instruction 156 add sv_pc, sv_pc, #-4 @ get call instruction address 176 * Test if the function start is a stmfd instruction to determine which 184 ldr r3, .Lopcode @ instruction exists,
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