intel/keembay/ocs-aes.c

195 	/* BPF JMP offset is relative to the next instruction */
200 	 * instruction offset.
236  * There are 3 types of AArch64 LDR/STR (immediate) instruction:
295 /* Offset of nop instruction in bpf prog entry to be poked */
340 	/* bpf function may be invoked by 3 instruction types:
804 	 * This is the relative offset of the instruction that may fault from
806 	 * table and if this instruction faults, the destination register will
807 	 * be set to '0' and the execution will jump to the next instruction.
821 	 * The fixup_offset is set to the next instruction from the instruction
850 /* JITs an eBPF instruction.
852  * 0  - successfully JITed an 8-byte eBPF instruction.
853  * >0 - successfully JITed a 16-byte eBPF instruction.
1262 		/* Optimization: when last instruction is EXIT,
1616 	 *   start of the 1st instruction.
1617 	 * - offset[1] - offset of the end of 1st instruction,
1618 	 *   start of the 2nd instruction
1620 	 * - offset[3] - offset of the end of 3rd instruction,
1621 	 *   start of 4th instruction
1642 	 * instruction (end of program)
1752 	 * instruction[i] in jited image, so build prologue first.
1920 		/* if cookie is zero, one instruction is enough to store it */
2107 	/* bpf trampoline may be invoked by 3 instruction types:
2361 /* Replace the branch instruction from @ip to @old_addr in a bpf prog or a bpf
2362  * trampoline with the branch instruction from @ip to @new_addr. If @old_addr
2363  * or @new_addr is NULL, the old or new instruction is NOP.
2388  * to a bl instruction to the trampoline directly:
2403  * the trampoline address and the patchsite is patched to a bl instruction to
2453 		/* skip to the nop instruction in bpf prog entry:
2497 		 * target value before fetching the bl instruction to plt,
2520 	/* We call aarch64_insn_patch_text_nosync() to replace instruction
2522 	 * instruction. But there is chance that another CPU executes the
2523 	 * old instruction after the patching operation finishes (e.g.,