/linux-master/drivers/clk/davinci/ |
H A D | pll-da830.c | 9 #include <linux/clk/davinci.h> 42 struct clk *clk; local 46 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); 47 clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0"); 48 clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1"); 50 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); 51 clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0"); 53 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); 54 clk_register_clkdev(clk, "pll0_sysclk [all...] |
/linux-master/sound/soc/fsl/ |
H A D | fsl_rpmsg.h | 35 struct clk *ipg; 36 struct clk *mclk; 37 struct clk *dma; 38 struct clk *pll8k; 39 struct clk *pll11k;
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/linux-master/drivers/clk/ti/ |
H A D | Makefile | 4 obj-y += clk.o autoidle.o clockdomain.o 5 clk-common = dpll.o composite.o divider.o gate.o \ 9 obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o 10 obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o 11 obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o 12 obj-$(CONFIG_ARCH_OMAP3) += $(clk [all...] |
H A D | clkt_dflt.c | 16 #include <linux/clk-provider.h> 18 #include <linux/clk/ti.h> 38 * @clk: module clock to wait for (needed for register offsets) 50 static int _wait_idlest_generic(struct clk_hw_omap *clk, argument 77 * @clk: struct clk * belonging to the module 80 * corresponds to clock @clk are enabled, then wait for the module to 85 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) argument 93 if (clk->ops->find_companion) { 94 clk 134 omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, struct clk_omap_reg *other_reg, u8 *other_bit) argument 163 omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, struct clk_omap_reg *idlest_reg, u8 *idlest_bit, u8 *idlest_val) argument 196 struct clk_hw_omap *clk; local 245 struct clk_hw_omap *clk; local 273 struct clk_hw_omap *clk = to_clk_hw_omap(hw); local [all...] |
H A D | autoidle.c | 10 #include <linux/clk-provider.h> 15 #include <linux/clk/ti.h> 39 static int _omap2_clk_deny_idle(struct clk_hw_omap *clk) argument 41 if (clk->ops && clk->ops->deny_idle) { 45 clk->autoidle_count++; 46 if (clk->autoidle_count == 1) 47 clk->ops->deny_idle(clk); 54 static int _omap2_clk_allow_idle(struct clk_hw_omap *clk) argument 75 omap2_clk_deny_idle(struct clk *clk) argument 99 omap2_clk_allow_idle(struct clk *clk) argument 117 _allow_autoidle(struct clk_ti_autoidle *clk) argument 131 _deny_autoidle(struct clk_ti_autoidle *clk) argument 187 struct clk_ti_autoidle *clk; local [all...] |
/linux-master/drivers/clk/sprd/ |
H A D | Makefile | 2 obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o 4 clk-sprd-y += common.o 5 clk-sprd-y += gate.o 6 clk-sprd-y += mux.o 7 clk-sprd-y += div.o 8 clk-sprd-y += composite.o 9 clk-sprd-y += pll.o 12 obj-$(CONFIG_SPRD_SC9860_CLK) += sc9860-clk.o 13 obj-$(CONFIG_SPRD_SC9863A_CLK) += sc9863a-clk.o 14 obj-$(CONFIG_SPRD_UMS512_CLK) += ums512-clk [all...] |
/linux-master/drivers/clk/sunxi/ |
H A D | Makefile | 3 # Makefile for sunxi specific clk 6 obj-$(CONFIG_CLK_SUNXI) += clk-factors.o 8 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sunxi.o 9 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-codec.o 10 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-hosc.o 11 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-mod1.o 12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o 13 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-ve.o 14 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a20-gmac.o 15 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk [all...] |
/linux-master/drivers/clk/samsung/ |
H A D | Makefile | 6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o 7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o 8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o 9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o 10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o 11 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5-subcmu.o 12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o 13 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk [all...] |
/linux-master/drivers/clk/spear/ |
H A D | spear3xx_clock.c | 9 #include <linux/clk.h> 11 #include <linux/clk/spear.h> 16 #include "clk.h" 141 struct clk *clk; local 143 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 145 clk_register_clkdev(clk, NULL, "60000000.clcd"); 147 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, 149 clk_register_clkdev(clk, NULL, "94000000.flash"); 151 clk 171 struct clk *clk; local 249 struct clk *clk; local 390 struct clk *clk, *clk1, *ras_apb_clk; local [all...] |
H A D | spear6xx_clock.c | 10 #include <linux/clk/spear.h> 13 #include "clk.h" 116 struct clk *clk, *clk1; local 118 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); 119 clk_register_clkdev(clk, "osc_32k_clk", NULL); 121 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); 122 clk_register_clkdev(clk, "osc_30m_clk", NULL); 124 /* clock derived from 32 KHz osc clk */ 125 clk [all...] |
H A D | spear1310_clock.c | 12 #include <linux/clk/spear.h> 16 #include "clk.h" 262 /* For gmac phy input clk */ 310 /* For parent clk = 49.152 MHz */ 317 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz 318 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz 322 /* For parent clk = 49.152 MHz */ 384 struct clk *clk, *clk1; local 386 clk [all...] |
/linux-master/drivers/clk/imx/ |
H A D | clk-imx5.c | 7 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 19 #include "clk.h" 128 static struct clk *clk[IMX5_CLK_END]; variable in typeref:struct:clk 133 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 134 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); 135 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); 136 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); 137 clk[IMX5_CLK_CKIH [all...] |
H A D | clk-imx1.c | 7 #include <linux/clk-provider.h> 15 #include "clk.h" 25 static struct clk *clk[IMX1_CLK_MAX]; variable in typeref:struct:clk 40 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 41 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768); 42 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); 43 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); 44 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); 45 clk[IMX1_CLK_PRE [all...] |
H A D | clk-imx31.c | 7 #include <linux/clk.h> 16 #include "clk.h" 50 static struct clk *clk[clk_max]; variable in typeref:struct:clk 55 clk[dummy] = imx_clk_fixed("dummy", 0); 56 clk[ckih] = imx_clk_fixed("ckih", fref); 57 clk[ckil] = imx_clk_fixed("ckil", 32768); 58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); 59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); 60 clk[upl [all...] |
H A D | clk-imx25.c | 9 #include <linux/clk.h> 18 #include "clk.h" 75 static struct clk *clk[clk_max]; variable in typeref:struct:clk 81 clk[dummy] = imx_clk_fixed("dummy", 0); 82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); 83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); 84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); 85 clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); 86 clk[cp [all...] |
/linux-master/drivers/clk/hisilicon/ |
H A D | Makefile | 6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o 8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o 9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o 10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o 12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o 13 obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o 14 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o 15 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o 17 obj-$(CONFIG_COMMON_CLK_HI6220) += clk [all...] |
/linux-master/drivers/clk/nuvoton/ |
H A D | Makefile | 2 obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1.o 3 obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o 4 obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o
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/linux-master/drivers/clk/stm32/ |
H A D | Makefile | 1 obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o 2 obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
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/linux-master/drivers/clk/uniphier/ |
H A D | Makefile | 2 obj-y += clk-uniphier-core.o 4 obj-y += clk-uniphier-cpugear.o 5 obj-y += clk-uniphier-fixed-factor.o 6 obj-y += clk-uniphier-fixed-rate.o 7 obj-y += clk-uniphier-gate.o 8 obj-y += clk-uniphier-mux.o 10 obj-y += clk-uniphier-sys.o 11 obj-y += clk-uniphier-mio.o 12 obj-y += clk-uniphier-peri.o
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/linux-master/drivers/clk/nxp/ |
H A D | Makefile | 2 obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o 3 obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-ccu.o 4 obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-creg.o 5 obj-$(CONFIG_ARCH_LPC32XX) += clk-lpc32xx.o
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/linux-master/arch/mips/loongson64/ |
H A D | time.c | 14 #include <linux/clk.h> 19 struct clk *clk; local 31 clk = of_clk_get(np, 0); 32 if (IS_ERR(clk)) { 33 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); 37 cpu_clock_freq = clk_get_rate(clk); 38 clk_put(clk);
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/linux-master/arch/m68k/include/asm/ |
H A D | mcfclk.h | 10 struct clk; 13 void (*enable)(struct clk *); 14 void (*disable)(struct clk *); 17 struct clk { struct 33 static struct clk __clk_##clk_bank##_##clk_slot = { \ 39 void __clk_init_enabled(struct clk *); 40 void __clk_init_disabled(struct clk *); 43 static struct clk clk_##clk_ref = { \
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/linux-master/drivers/clk/microchip/ |
H A D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o 3 obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o 4 obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs.o 5 obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs-ccc.o
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/linux-master/drivers/clk/starfive/ |
H A D | Makefile | 2 obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o 4 obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o 5 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o 7 obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o 8 obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o 9 obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o 10 obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o 11 obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o 12 obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
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/linux-master/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7780.c | 22 static void master_clk_init(struct clk *clk) argument 24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; 31 static unsigned long module_clk_recalc(struct clk *clk) argument 34 return clk->parent->rate / pfc_divisors[idx]; 41 static unsigned long bus_clk_recalc(struct clk *clk) argument 44 return clk->parent->rate / bfc_divisors[idx]; 51 static unsigned long cpu_clk_recalc(struct clk *cl argument 74 shyway_clk_recalc(struct clk *clk) argument 104 struct clk *clk; local [all...] |