| /linux-master/arch/arm/mm/ |
| H A D | tlb-fa.S | 36 vma_vm_mm ip, r2
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| H A D | tlb-v4wb.S | 32 vma_vm_mm ip, r2
36 vma_vm_flags r2, r2
38 tst r2, #VM_EXEC
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| H A D | tlb-v4.S | 32 vma_vm_mm ip, r2
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| H A D | proc-xscale.S | 213 mov r2, #VM_EXEC
217 tst r2, #VM_EXEC
240 1: tst r2, #VM_EXEC
247 tst r2, #VM_EXEC
391 cmp r2, #DMA_TO_DEVICE
419 teq r2, #DMA_TO_DEVICE
453 clean_d_cache r1, r2
500 bic r2, r2, #0x0c
501 orr r2, r
[all...] |
| H A D | proc-v7.S | 58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
59 bic r2, r2, #0x1 @ ...............m
60 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
88 1: dcache_line_size r2, r3
90 add r0, r0, r2
91 subs r1, r1, r2
269 mov r7, r2
[all...] |
| H A D | proc-xsc3.S | 171 mov r2, #VM_EXEC
175 tst r2, #VM_EXEC
199 1: tst r2, #VM_EXEC
205 tst r2, #VM_EXEC
333 cmp r2, #DMA_TO_DEVICE
368 clean_d_cache r1, r2
409 orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
410 bic r2, r2, #
[all...] |
| H A D | proc-v7m.S | 76 dcache_line_size r2, r3
81 add r0, r0, r2
82 subs r1, r1, r2
89 movw r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
90 movt r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
91 ldr r0, [r2]
93 str r0, [r2]
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| H A D | proc-v6.S | 105 mov r2, #0
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
113 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
114 bic r2, r2, #0xff @ extract the PID
116 orr r1, r1, r2 @ insert into new context ID
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| H A D | proc-v7-3level.S | 47 mmid r2, r2
48 asid r2, r2
49 orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd
58 #define rh r2
60 #define rl r2
69 * - pte - PTE value to store (64-bit in r2 and r3)
85 1: strd r2, r3, [r0]
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| H A D | proc-v7-2level.S | 49 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
50 lsr r2, r2, #8 @ extract the PID
51 bfi r1, r2, #8, #24 @ insert into new context ID
80 orr r3, r3, r2
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| H A D | proc-macros.S | 158 orr r3, r3, r2
162 and r2, r1, #L_PTE_MT_MASK
163 ldr r2, [ip, r2]
179 eor r3, r3, r2
211 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
212 bic r2, r2, #PTE_TYPE_MASK
213 orr r2, r2, #PTE_TYPE_SMAL
[all...] |
| H A D | proc-mohawk.S | 114 mov r2, #VM_EXEC
118 tst r2, #VM_EXEC
141 1: tst r2, #VM_EXEC
150 tst r2, #VM_EXEC
288 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-feroceon.S | 50 mov r2, #(16 << 5)
56 mov r2, r2, lsl r0 @ actual cache size
57 movne r2, r2, lsr #2 @ turned into # of sets
58 sub r2, r2, #(1 << 5)
59 stmia r1, {r2, r3}
62 str_l r1, VFP_arch_feroceon, r2
150 mov r2, #VM_EXE
[all...] |
| H A D | proc-arm926.S | 95 bic r2, r1, #1 << 12
99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
131 mov r2, #VM_EXEC
140 tst r2, #VM_EXEC
161 1: tst r2, #VM_EXEC
179 tst r2, #VM_EXEC
323 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm946.S | 105 mov r2, #VM_EXEC
119 tst r2, #VM_EXEC
142 1: tst r2, #VM_EXEC
160 tst r2, #VM_EXEC
307 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm940.S | 98 mov r2, #VM_EXEC
125 tst r2, #VM_EXEC
265 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm925.S | 133 bic r2, r1, #1 << 12
134 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
165 mov r2, #VM_EXEC
177 tst r2, #VM_EXEC
198 1: tst r2, #VM_EXEC
216 tst r2, #VM_EXEC
360 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm920.S | 129 mov r2, #VM_EXEC
139 tst r2, #VM_EXEC
162 tst r2, #VM_EXEC
167 tst r2, #VM_EXEC
302 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm922.S | 131 mov r2, #VM_EXEC
141 tst r2, #VM_EXEC
164 tst r2, #VM_EXEC
169 tst r2, #VM_EXEC
304 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm1026.S | 141 mov r2, #VM_EXEC
148 tst r2, #VM_EXEC
178 tst r2, #VM_EXEC
332 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm1020.S | 141 mov r2, #VM_EXEC
155 tst r2, #VM_EXEC
187 tst r2, #VM_EXEC
351 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm1020e.S | 141 mov r2, #VM_EXEC
154 tst r2, #VM_EXEC
184 tst r2, #VM_EXEC
338 cmp r2, #DMA_TO_DEVICE
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| H A D | proc-arm1022.S | 141 mov r2, #VM_EXEC
153 tst r2, #VM_EXEC
183 tst r2, #VM_EXEC
337 cmp r2, #DMA_TO_DEVICE
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| H A D | cache-v7m.S | 128 and r2, r1, r0, lsr #13
133 add r2, r2, #1 @ NumSets
140 1: sub r2, r2, #1 @ NumSets--
144 mov r6, r2, lsl r0
148 cmp r2, #0
184 add r2, r10, r10, lsr #1 @ work out 3x current cache level
185 mov r1, r0, lsr r2 @ extract cache type bits from clidr
198 and r2, r
[all...] |
| H A D | cache-v7.S | 51 mov r2, #1
53 movs r1, r2, lsl r1 @ #1 shifted left by same amount
56 and r2, r0, #0x7
57 add r2, r2, #4 @ SetShift
62 2: mov ip, r0, lsl r2 @ NumSet << SetShift
107 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
111 teq r1, r2, lsr #4 @ test for errata affected core and if so...
136 add r2, r10, r10, lsr #1 @ work out 3x current cache level
137 mov r1, r0, lsr r2
[all...] |