Searched refs:val (Results 226 - 250 of 10961) sorted by relevance

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/linux-master/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy_28nm_8960.xml.h85 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) argument
87 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
93 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) argument
95 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
101 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) argument
103 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
111 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) argument
113 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
119 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) argument
121 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIF
127 DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) argument
135 DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) argument
143 DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) argument
151 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) argument
157 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) argument
165 DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) argument
173 DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) argument
[all...]
H A Ddsi_phy_20nm.xml.h97 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) argument
99 return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
105 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) argument
107 return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
113 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) argument
115 return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
124 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) argument
126 return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
132 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) argument
134 return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIF
140 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) argument
148 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) argument
156 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) argument
164 DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) argument
170 DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) argument
178 DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) argument
186 DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) argument
[all...]
/linux-master/arch/powerpc/sysdev/
H A Dgrackle.c25 unsigned int val; local
28 val = in_le32(bp->cfg_data);
29 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
30 (val & ~GRACKLE_PICR1_LOOPSNOOP);
32 out_le32(bp->cfg_data, val);
/linux-master/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_pcode.h13 snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, argument
16 return xe_pcode_write_timeout(__compat_uncore_to_gt(uncore), mbox, val,
21 snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val) argument
24 return xe_pcode_write(__compat_uncore_to_gt(uncore), mbox, val);
28 snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1) argument
30 return xe_pcode_read(__compat_uncore_to_gt(uncore), mbox, val, val1);
/linux-master/sound/soc/hisilicon/
H A Dhi6210-i2s.c80 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val) argument
82 writel(val, i2s->base + reg);
95 u32 val; local
98 regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
99 if (val & BIT(4))
126 val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
127 val |= 0x3f;
128 hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
132 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
133 val |
186 u32 val; local
206 u32 val; local
259 u32 val; local
[all...]
/linux-master/arch/parisc/include/asm/
H A Dspecial_insns.h54 #define set_eiem(val) mtctl(val, CR_EIEM)
65 #define mtsp(val, cr) \
66 { if (__builtin_constant_p(val) && ((val) == 0)) \
71 : "r" (val), "i" (cr) : "memory"); }
/linux-master/security/selinux/ss/
H A Dsymtab.c17 unsigned int val; local
19 val = 0;
23 val = (val << 4 | (val >> (8 * sizeof(unsigned int) - 4))) ^
25 return val;
/linux-master/drivers/tty/serial/
H A Dbcm63xx_uart.c90 unsigned int val; local
92 val = bcm_uart_readl(port, UART_IR_REG);
93 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
101 unsigned int val; local
103 val = bcm_uart_readl(port, UART_MCTL_REG);
104 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
107 val |= UART_MCTL_DTR_MASK;
109 val |= UART_MCTL_RTS_MASK;
110 bcm_uart_writel(port, val, UART_MCTL_REG);
112 val
125 unsigned int val, mctrl; local
145 unsigned int val; local
161 unsigned int val; local
177 unsigned int val; local
189 unsigned int val; local
202 unsigned int val; local
245 unsigned int val; local
305 unsigned int val; local
364 unsigned int val; local
376 unsigned int val; local
389 unsigned int val; local
406 unsigned int val; local
604 unsigned int val; local
666 unsigned int val; local
678 unsigned int val; local
[all...]
/linux-master/drivers/net/ethernet/qualcomm/emac/
H A Demac-mac.h42 #define BITS_GET(val, lo, hi) ((le32_to_cpu(val) & GENMASK((hi), (lo))) >> lo)
43 #define BITS_SET(val, lo, hi, new_val) \
44 val = cpu_to_le32((le32_to_cpu(val) & (~GENMASK((hi), (lo)))) | \
67 #define RRD_UPDT_SET(rrd, val) BITS_SET((rrd)->word[3], 31, 31, val)
79 #define TPD_BUF_LEN_SET(tpd, val) BITS_SET((tpd)->word[0], 0, 15, val)
81 #define TPD_CSX_SET(tpd, val) BITS_SE
[all...]
/linux-master/drivers/clk/imx/
H A Dclk-frac-pll.c46 u32 val; local
48 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
54 u32 val; local
61 return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
68 u32 val; local
70 val = readl_relaxed(pll->base + PLL_CFG0);
71 val &= ~PLL_PD_MASK;
72 writel_relaxed(val, pl
80 u32 val; local
90 u32 val; local
100 u32 val, divff, divfi, divq; local
159 u32 val, divfi, divff; local
[all...]
/linux-master/drivers/comedi/drivers/
H A Dc6xdigio.c63 unsigned int val, unsigned int status)
65 outb_p(val, dev->iobase + C6XDIGIO_DATA_REG);
74 unsigned int val; local
76 val = inb(dev->iobase + C6XDIGIO_STATUS_REG);
77 val >>= 3;
78 val &= 0x07;
80 *bits = val;
86 unsigned int chan, unsigned int val)
91 if (val > 498)
92 val
62 c6xdigio_write_data(struct comedi_device *dev, unsigned int val, unsigned int status) argument
85 c6xdigio_pwm_write(struct comedi_device *dev, unsigned int chan, unsigned int val) argument
114 unsigned int val = 0; local
154 unsigned int val = (s->state >> (16 * chan)) & 0xffff; local
180 unsigned int val; local
197 unsigned int val; local
[all...]
/linux-master/drivers/media/i2c/ccs/
H A Dccs-reg-access.c65 static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val) argument
67 if (val >> 10 > U32_MAX / 15625) {
68 dev_warn(&client->dev, "value %u overflows!\n", val);
72 return ((val >> 10) * 15625) +
73 (val & GENMASK(9, 0)) * 15625 / 1024;
76 u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val) argument
83 val = ireal32_to_u32_mul_1000000(client, val);
85 val = float_to_u32_mul_1000000(client, val);
97 __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val, bool only8, bool conv) argument
112 __ccs_static_data_read_ro_reg(struct ccs_reg *regs, size_t num_regs, u32 reg, u32 *val) argument
151 ccs_static_data_read_ro_reg(struct ccs_sensor *sensor, u32 reg, u32 *val) argument
163 ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, bool force8, bool quirk, bool conv, bool data) argument
192 ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val) argument
197 ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val) argument
202 ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val) argument
211 ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val) argument
[all...]
/linux-master/arch/mips/loongson2ef/lemote-2f/
H A Dreset.c53 u32 hi, lo, val; local
61 val = inl(gpio_base + GPIOL_OUT_EN);
62 val &= ~(1 << (16 + 13));
63 val |= (1 << 13);
64 outl(val, gpio_base + GPIOL_OUT_EN);
67 val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
68 val |= (1 << (16 + 13));
69 outl(val, gpio_base + GPIOL_OUT_VAL);
95 u8 val; local
101 val
[all...]
/linux-master/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_magn.h26 int *val, int *val2)
28 *val = 0;
37 int inv_mpu_magn_read(struct inv_mpu6050_state *st, int axis, int *val);
24 inv_mpu_magn_get_scale(const struct inv_mpu6050_state *st, const struct iio_chan_spec *chan, int *val, int *val2) argument
/linux-master/tools/perf/bench/
H A Dfutex.h34 * @val: typically expected value of uaddr, but varies by op
49 futex_syscall(volatile u_int32_t *uaddr, int op, u_int32_t val, struct timespec *timeout, argument
52 return syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3);
56 futex_syscall_nr_requeue(volatile u_int32_t *uaddr, int op, u_int32_t val, int nr_requeue, argument
59 return syscall(SYS_futex, uaddr, op | opflags, val, nr_requeue, uaddr2, val3);
67 futex_wait(u_int32_t *uaddr, u_int32_t val, struct timespec *timeout, int opflags) argument
69 return futex_syscall(uaddr, FUTEX_WAIT, val, timeout, NULL, 0, opflags);
106 futex_cmp_requeue(u_int32_t *uaddr, u_int32_t val, u_int32_t *uaddr2, int nr_wake, argument
110 val, opflags);
122 futex_wait_requeue_pi(u_int32_t *uaddr, u_int32_t val, u_int32_ argument
139 futex_cmp_requeue_pi(u_int32_t *uaddr, u_int32_t val, u_int32_t *uaddr2, int nr_requeue, int opflags) argument
[all...]
/linux-master/net/ipv4/
H A Dmetrics.c20 u32 val; local
34 val = tcp_ca_get_key_by_name(net, tmp, &ecn_ca);
35 if (val == TCP_CA_UNSPEC) {
45 val = nla_get_u32(nla);
47 if (type == RTAX_ADVMSS && val > 65535 - 40)
48 val = 65535 - 40;
49 if (type == RTAX_MTU && val > 65535 - 15)
50 val = 65535 - 15;
51 if (type == RTAX_HOPLIMIT && val > 255)
52 val
[all...]
/linux-master/arch/mips/boot/compressed/
H A Ddbg.c28 void puthex(unsigned long long val) argument
34 buf[i] = "0123456789ABCDEF"[val & 0x0F];
35 val >>= 4;
/linux-master/arch/s390/include/asm/
H A Dpreempt.h47 static __always_inline void __preempt_count_add(int val) argument
54 if (__builtin_constant_p(val) && (val >= -128) && (val <= 127)) {
55 __atomic_add_const(val, &S390_lowcore.preempt_count);
59 __atomic_add(val, &S390_lowcore.preempt_count);
62 static __always_inline void __preempt_count_sub(int val) argument
64 __preempt_count_add(-val);
105 static __always_inline void __preempt_count_add(int val) argument
107 S390_lowcore.preempt_count += val;
110 __preempt_count_sub(int val) argument
[all...]
/linux-master/arch/x86/kernel/
H A Dquirks.c75 u32 val; local
83 val = readl(rcba_base + 0x3404);
84 if (!(val & 0x80)) {
86 writel(val | 0x80, rcba_base + 0x3404);
89 val = readl(rcba_base + 0x3404);
90 if (!(val & 0x80))
98 u32 val; local
122 val = readl(rcba_base + 0x3404);
124 if (val & 0x80) {
126 val
188 u32 val; local
210 u32 val; local
285 u32 val; local
302 u32 val; local
380 u32 d, val; local
433 u32 val; local
542 u32 val; local
606 u32 val; local
[all...]
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-artpec6.c86 u32 val; local
88 regmap_read(artpec6_pcie->regmap, offset, &val);
89 return val;
92 static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val) argument
94 regmap_write(artpec6_pcie->regmap, offset, val);
117 u32 val; local
119 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
120 val |= PCIECFG_LTSSM_ENABLE;
121 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
129 u32 val; local
146 u32 val; local
173 u32 val; local
213 u32 val; local
244 u32 val; local
287 u32 val; local
303 u32 val; local
386 u32 val; local
[all...]
/linux-master/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) argument
122 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) argument
128 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) argument
150 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) argument
156 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) argument
162 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIF
190 MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) argument
197 MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) argument
204 MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) argument
211 MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) argument
218 MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) argument
225 MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) argument
232 MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) argument
239 MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) argument
250 MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) argument
257 MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) argument
264 MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) argument
271 MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) argument
278 MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) argument
285 MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) argument
292 MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) argument
299 MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) argument
333 MDP4_OVLP_SIZE_HEIGHT(uint32_t val) argument
339 MDP4_OVLP_SIZE_WIDTH(uint32_t val) argument
365 MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) argument
373 MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) argument
468 MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) argument
474 MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) argument
480 MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) argument
487 MDP4_DMA_CONFIG_PACK(uint32_t val) argument
497 MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) argument
503 MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) argument
515 MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) argument
521 MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) argument
529 MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) argument
535 MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) argument
545 MDP4_DMA_CURSOR_POS_X(uint32_t val) argument
551 MDP4_DMA_CURSOR_POS_Y(uint32_t val) argument
560 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) argument
602 MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) argument
608 MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) argument
616 MDP4_PIPE_SRC_XY_Y(uint32_t val) argument
622 MDP4_PIPE_SRC_XY_X(uint32_t val) argument
630 MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) argument
636 MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) argument
644 MDP4_PIPE_DST_XY_Y(uint32_t val) argument
650 MDP4_PIPE_DST_XY_X(uint32_t val) argument
666 MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) argument
672 MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) argument
680 MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) argument
686 MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) argument
694 MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) argument
700 MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) argument
708 MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) argument
714 MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) argument
720 MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) argument
726 MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) argument
733 MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) argument
740 MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) argument
748 MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) argument
755 MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) argument
761 MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) argument
769 MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) argument
775 MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) argument
781 MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) argument
787 MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) argument
797 MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) argument
803 MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) argument
855 MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) argument
861 MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) argument
873 MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) argument
879 MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) argument
891 MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) argument
897 MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) argument
912 MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) argument
950 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) argument
956 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) argument
962 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) argument
968 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) argument
976 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) argument
982 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) argument
988 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) argument
1029 MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) argument
1035 MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) argument
1047 MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) argument
1053 MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) argument
1065 MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) argument
1071 MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) argument
1086 MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) argument
1108 MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) argument
1114 MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) argument
1126 MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) argument
1132 MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) argument
1144 MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) argument
1150 MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) argument
1165 MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) argument
[all...]
/linux-master/drivers/clk/meson/
H A Dvid-pll-div.h14 struct parm val; member in struct:meson_vid_pll_div_data
/linux-master/arch/mips/boot/tools/
H A Drelocs_64.c25 #define ELF_R_SYM(val) (((Elf64_Mips_Rela *)(&val))->fields.r_sym)
26 #define ELF_R_TYPE(val) (((Elf64_Mips_Rela *)(&val))->fields.r_type)
/linux-master/arch/mips/jazz/
H A Dreset.c13 static void jazz_write_output(unsigned char val) argument
20 jazz_kh->data = val;
23 static void jazz_write_command(unsigned char val) argument
30 jazz_kh->command = val;
/linux-master/arch/arm/include/asm/
H A Dkrait-l2-accessors.h6 extern void krait_set_l2_indirect_reg(u32 addr, u32 val);

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