Lines Matching refs:val
80 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
82 writel(val, i2s->base + reg);
95 u32 val;
98 regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
99 if (val & BIT(4))
126 val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
127 val |= 0x3f;
128 hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
132 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
133 val |= (BIT(5) | BIT(4));
134 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
136 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
137 val &= ~(BIT(5) | BIT(4));
138 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
141 val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
142 val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
144 val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
145 hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
147 val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
149 val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
151 val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
152 val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
154 val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
156 val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
157 hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
159 val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
160 val |= HII2S_SW_RST_N__SW_RST_N;
161 hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
186 u32 val;
191 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
192 val |= HII2S_I2S_CFG__S2_IF_TX_EN;
193 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
196 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
197 val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
198 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
206 u32 val;
210 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
211 val |= HII2S_I2S_CFG__S2_IF_RX_EN;
212 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
214 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
215 val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
216 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
259 u32 val;
326 val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
327 val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
335 val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
339 hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
342 val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
343 val |= (BIT(19) | BIT(18) | BIT(17) |
349 hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
352 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
353 val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
359 val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
361 hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
364 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
365 val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
367 hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
369 val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
370 val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
374 hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
380 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
381 val |= HII2S_I2S_CFG__S2_MST_SLV;
382 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
386 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
387 val &= ~HII2S_I2S_CFG__S2_MST_SLV;
388 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
410 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
411 val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
413 val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
414 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
417 val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
418 val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
420 hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
431 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
432 val |= HII2S_I2S_CFG__S2_FRAME_MODE;
433 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
436 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
437 val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
438 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
443 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
444 val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
445 val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
447 val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
449 val |= signed_data;
450 val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
451 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
458 val = hi6210_read_reg(i2s, HII2S_FS_CFG);
459 val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
460 val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
461 val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
463 val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
465 val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
466 val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
467 val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
468 val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
469 hi6210_write_reg(i2s, HII2S_FS_CFG, val);