Searched refs:reg (Results 226 - 250 of 313) sorted by relevance

1234567891011>>

/haiku/src/add-ons/kernel/drivers/audio/ac97/auvia/
H A Dmulti.c56 value = auvia_codec_read(&dev->config, info->reg);
83 value = auvia_codec_read(&dev->config, info->reg);
90 value = auvia_codec_read(&dev->config, info->reg);
114 value = auvia_codec_read(&dev->config, info->reg);
142 auvia_codec_write(&dev->config, info->reg, value);
146 value = auvia_codec_read(&dev->config, info->reg);
149 if (info->reg == AC97_SURR_VOLUME) {
156 auvia_codec_write(&dev->config, info->reg, value);
160 value = auvia_codec_read(&dev->config, info->reg);
164 auvia_codec_write(&dev->config, info->reg, valu
[all...]
/haiku/src/add-ons/kernel/drivers/audio/ac97/geode/
H A Dgeode_multi.cpp195 value = ac97_reg_cached_read(controller->ac97, info->reg);
222 value = ac97_reg_cached_read(controller->ac97, info->reg);
229 value = ac97_reg_cached_read(controller->ac97, info->reg);
253 value = ac97_reg_cached_read(controller->ac97, info->reg);
281 ac97_reg_cached_write(controller->ac97, info->reg, value);
285 value = ac97_reg_cached_read(controller->ac97, info->reg);
288 if (info->reg == AC97_SURR_VOLUME) {
295 ac97_reg_cached_write(controller->ac97, info->reg, value);
299 value = ac97_reg_cached_read(controller->ac97, info->reg);
303 ac97_reg_cached_write(controller->ac97, info->reg, valu
[all...]
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_eeprom.c555 ** \param reg register being inspected on this call
562 u_int32_t reg, u_int32_t value)
577 if ( reg == 0x7894 )
947 * MIN( TPC reg, BB_powertx_rate register)
1459 unsigned long reg; local
1463 reg = OS_REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
1464 reg &= ~0x00ffffc0;
1465 reg |= 0x5 << 21;
1466 reg |= 0x5 << 18;
1467 reg |
561 ar9300_ini_fixup(struct ath_hal *ah, ar9300_eeprom_t *p_eep_data, u_int32_t reg, u_int32_t value) argument
[all...]
H A Dar9300_interrupts.c738 HAL_INT_MITIGATION reg,
742 switch (reg) {
765 ar9300_get_intr_mitigation_timer(struct ath_hal* ah, HAL_INT_MITIGATION reg) argument
769 switch (reg) {
736 ar9300_set_intr_mitigation_timer( struct ath_hal* ah, HAL_INT_MITIGATION reg, u_int32_t value) argument
/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/
H A Dif_rtwn.c649 uint32_t reg; local
651 reg = rtwn_read_4(sc, R92C_SYS_CFG);
652 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) /* test chip */
655 rtwn_read_chipid_vendor(sc, reg);
976 uint32_t reg; local
978 reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL);
980 reg |= R92C_WMAC_TRXPTCL_SHPRE;
982 reg &= ~R92C_WMAC_TRXPTCL_SHPRE;
983 rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg);
1386 uint16_t reg; local
[all...]
/haiku/src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/
H A Dif_rgereg.h429 #define RGE_WRITE_4(sc, reg, val) \
430 bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)
431 #define RGE_WRITE_2(sc, reg, val) \
432 bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val)
433 #define RGE_WRITE_1(sc, reg, val) \
434 bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)
436 #define RGE_READ_4(sc, reg) \
437 bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg)
438 #define RGE_READ_2(sc, reg) \
439 bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg)
476 uint16_t reg; member in struct:__anon13
592 uint16_t reg; member in struct:__anon14
[all...]
/haiku/src/kits/debugger/controllers/
H A DDebugReportGenerator.cpp637 const Register* reg = NULL; local
639 reg = fArchitecture->Registers() + i;
640 state->GetRegisterValue(reg, value);
642 if (reg->Format() == REGISTER_FORMAT_SIMD) {
643 data.SetToFormat("\t\t\t%5s:\t%s\n", reg->Name(),
644 UiUtils::FormatSIMDValue(value, reg->BitSize(),
648 data.SetToFormat("\t\t\t%5s:\t%s\n", reg->Name(),
/haiku/src/kits/debugger/debug_info/
H A DDwarfTypes.cpp404 int32 reg = typeContext->FromDwarfRegisterMap()->MapRegisterIndex( local
405 piece.reg);
406 if (reg >= 0) {
407 piece.reg = reg;
411 if (registers[reg].BitSize() > piece.bitSize) {
412 piece.bitOffset = registers[reg].BitSize() - piece.bitSize
/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/
H A Dif_iwnreg.h2335 #define IWN_READ(sc, reg) \
2336 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
2338 #define IWN_WRITE(sc, reg, val) \
2339 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
2341 #define IWN_WRITE_1(sc, reg, val) \
2342 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
2344 #define IWN_SETBITS(sc, reg, mask) \
2345 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
2347 #define IWN_CLRBITS(sc, reg, mas
[all...]
/haiku/src/add-ons/kernel/drivers/network/ether/ipro1000/dev/e1000/
H A De1000_phy.h166 #define BM_PHY_REG(page, reg) \
167 (((reg) & MAX_PHY_REG_ADDRESS) |\
169 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
H A De1000_phy.c3101 * @reg: register to access
3105 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) argument
3109 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3445 u16 reg = BM_PHY_REG_NUM(offset); local
3451 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3461 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3466 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3469 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3550 u16 reg = BM_PHY_REG_NUM(offset); local
3660 u16 reg = BM_PHY_REG_NUM(offset); local
[all...]
H A De1000_mac.h80 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
/haiku/src/add-ons/kernel/busses/usb/
H A Duhci.cpp778 TRACE("usbcmd reg 0x%04x, usbsts reg 0x%04x\n",
2483 UHCI::WriteReg8(uint32 reg, uint8 value) argument
2485 fPci->write_io_8(fDevice, fRegisterBase + reg, value);
2490 UHCI::WriteReg16(uint32 reg, uint16 value) argument
2492 fPci->write_io_16(fDevice, fRegisterBase + reg, value);
2497 UHCI::WriteReg32(uint32 reg, uint32 value) argument
2499 fPci->write_io_32(fDevice, fRegisterBase + reg, value);
2504 UHCI::ReadReg8(uint32 reg) argument
2506 return fPci->read_io_8(fDevice, fRegisterBase + reg);
2511 ReadReg16(uint32 reg) argument
2518 ReadReg32(uint32 reg) argument
[all...]
/haiku/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/
H A Drt2661.c176 uint32_t reg; member in struct:__anon6
183 uint8_t reg; member in struct:__anon7
1690 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) argument
1705 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
1708 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
1712 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) argument
1727 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
1742 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) argument
1758 (reg & 3);
1762 sc->rf_regs[reg]
[all...]
H A Drt2860var.h188 uint8_t reg; member in struct:rt2860_softc::__anon13
H A Drt2560.c170 uint32_t reg; member in struct:__anon2
177 uint8_t reg; member in struct:__anon3
1953 rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val) argument
1968 tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
1971 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
1975 rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg) argument
1990 val = RT2560_BBP_BUSY | reg << 8;
2005 rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val) argument
2021 (reg & 0x3);
2025 sc->rf_regs[reg]
[all...]
/haiku/src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/
H A Dif_msk.c402 msk_miibus_readreg(device_t dev, int phy, int reg) argument
408 return (msk_phy_readreg(sc_if, phy, reg));
412 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) argument
420 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
440 msk_miibus_writereg(device_t dev, int phy, int reg, int val) argument
446 return (msk_phy_writereg(sc_if, phy, reg, val));
450 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) argument
459 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
1438 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1746 int error, msic, msir, reg; local
3814 uint32_t reg; local
4326 uint32_t reg; local
4351 uint32_t reg; local
[all...]
/haiku/src/add-ons/accelerants/via/engine/
H A Dgeneral.c17 #define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \
18 uint32 value = CFGR(reg); \
20 ENCFG_##reg, #reg, value)); \
/haiku/src/libs/compat/freebsd_network/compat/machine/x86_64/
H A Dcpufunc.h473 rxcr(u_int reg) argument
477 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
482 load_xcr(u_int reg, u_long val) argument
488 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
/haiku/src/libs/compat/freebsd_network/
H A Dfbsd_mii.c290 miibus_readreg(device_t dev, int phy, int reg) argument
295 return (MIIBUS_READREG(parent, phy, reg));
299 miibus_writereg(device_t dev, int phy, int reg, int data) argument
304 return (MIIBUS_WRITEREG(parent, phy, reg, data));
/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi2200/dev/iwi/
H A Dif_iwivar.h98 uint32_t reg; member in struct:iwi_rx_data
/haiku/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/usb/wlan/
H A Dif_rumvar.h157 uint8_t reg; member in struct:rum_softc::__anon4
/haiku/src/add-ons/kernel/bus_managers/acpi/
H A DACPICAHaiku.cpp889 * reg Device Register
899 AcpiOsReadPciConfiguration(ACPI_PCI_ID *pciId, UINT32 reg, UINT64 *value, argument
910 pciId->Bus, pciId->Device, pciId->Function, reg, width / 8);
927 * reg Device Register
937 AcpiOsWritePciConfiguration(ACPI_PCI_ID *pciId, UINT32 reg, argument
943 pciId->Bus, pciId->Device, pciId->Function, reg, width / 8, value);
/haiku/src/add-ons/kernel/drivers/audio/hda/
H A Dhda_controller.cpp190 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, argument
201 value = base->Read8(reg);
204 value = base->Read16(reg);
207 value = base->Read32(reg);
220 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, argument
224 controller->pci_info.device, controller->pci_info.function, reg, size);
227 reg, size, (originalValue & mask) | value);
233 controller->pci_info.device, controller->pci_info.function, reg, size);
/haiku/src/add-ons/kernel/drivers/network/ether/dec21xxx/dev/dc/
H A Dif_dcreg.h807 #define CSR_WRITE_4(sc, reg, val) \
808 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
810 #define CSR_READ_4(sc, reg) \
811 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
813 #define CSR_BARRIER_4(sc, reg, flags) \
814 bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags)

Completed in 346 milliseconds

1234567891011>>