1/* $FreeBSD: releng/12.0/sys/dev/iwn/if_iwnreg.h 315958 2017-03-25 15:57:47Z avos $ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20#ifndef __IF_IWNREG_H__ 21#define __IF_IWNREG_H__ 22 23#define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 24#define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 25 26#define IWN_TX_RING_COUNT 256 27#define IWN_TX_RING_LOMARK 192 28#define IWN_TX_RING_HIMARK 224 29#define IWN_RX_RING_COUNT_LOG 6 30#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31 32#define IWN4965_NTXQUEUES 16 33#define IWN5000_NTXQUEUES 20 34 35#define IWN4965_FIRSTAGGQUEUE 7 36#define IWN5000_FIRSTAGGQUEUE 10 37 38#define IWN4965_NDMACHNLS 7 39#define IWN5000_NDMACHNLS 8 40 41#define IWN_SRVC_DMACHNL 9 42 43#define IWN_ICT_SIZE 4096 44#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 45 46/* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 47#define IWN_CMD_QUEUE_NUM 4 48#define IWN_PAN_CMD_QUEUE 9 49 50/* Maximum number of DMA segments for TX. */ 51#define IWN_MAX_SCATTER 20 52 53/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 54#define IWN_RBUF_SIZE (4 * 1024) 55 56#if defined(__LP64__) 57/* HW supports 36-bit DMA addresses. */ 58#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 59#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 60#else 61#define IWN_LOADDR(paddr) (paddr) 62#define IWN_HIADDR(paddr) (0) 63#endif 64 65/* 66 * Control and status registers. 67 */ 68#define IWN_HW_IF_CONFIG 0x000 69#define IWN_INT_COALESCING 0x004 70#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 71#define IWN_INT 0x008 72#define IWN_INT_MASK 0x00c 73#define IWN_FH_INT 0x010 74#define IWN_GPIO_IN 0x018 /* read external chip pins */ 75#define IWN_RESET 0x020 76#define IWN_GP_CNTRL 0x024 77#define IWN_HW_REV 0x028 78#define IWN_EEPROM 0x02c 79#define IWN_EEPROM_GP 0x030 80#define IWN_OTP_GP 0x034 81#define IWN_GIO 0x03c 82#define IWN_GP_UCODE 0x048 83#define IWN_GP_DRIVER 0x050 84#define IWN_UCODE_GP1 0x054 85#define IWN_UCODE_GP1_SET 0x058 86#define IWN_UCODE_GP1_CLR 0x05c 87#define IWN_UCODE_GP2 0x060 88#define IWN_LED 0x094 89#define IWN_DRAM_INT_TBL 0x0a0 90#define IWN_SHADOW_REG_CTRL 0x0a8 91#define IWN_GIO_CHICKEN 0x100 92#define IWN_ANA_PLL 0x20c 93#define IWN_HW_REV_WA 0x22c 94#define IWN_DBG_HPET_MEM 0x240 95#define IWN_DBG_LINK_PWR_MGMT 0x250 96/* Need nic_lock for use above */ 97#define IWN_MEM_RADDR 0x40c 98#define IWN_MEM_WADDR 0x410 99#define IWN_MEM_WDATA 0x418 100#define IWN_MEM_RDATA 0x41c 101#define IWN_TARG_MBX_C 0x430 102#define IWN_PRPH_WADDR 0x444 103#define IWN_PRPH_RADDR 0x448 104#define IWN_PRPH_WDATA 0x44c 105#define IWN_PRPH_RDATA 0x450 106#define IWN_HBUS_TARG_WRPTR 0x460 107 108/* 109 * Flow-Handler registers. 110 */ 111#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 112#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 113#define IWN_FH_KW_ADDR 0x197c 114#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 115#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 116#define IWN_FH_STATUS_WPTR 0x1bc0 117#define IWN_FH_RX_BASE 0x1bc4 118#define IWN_FH_RX_WPTR 0x1bc8 119#define IWN_FH_RX_CONFIG 0x1c00 120#define IWN_FH_RX_STATUS 0x1c44 121#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 122#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 123#define IWN_FH_TX_CHICKEN 0x1e98 124#define IWN_FH_TX_STATUS 0x1eb0 125 126/* 127 * TX scheduler registers. 128 */ 129#define IWN_SCHED_BASE 0xa02c00 130#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 131#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 132#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 133#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 134#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 135#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 136#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 137#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 138#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 139#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 140#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 141#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 142#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 143#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 144 145/* 146 * Offsets in TX scheduler's SRAM. 147 */ 148#define IWN4965_SCHED_CTX_OFF 0x380 149#define IWN4965_SCHED_CTX_LEN 416 150#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 151#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 152#define IWN5000_SCHED_CTX_OFF 0x600 153#define IWN5000_SCHED_CTX_LEN 520 154#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 155#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 156 157/* 158 * NIC internal memory offsets. 159 */ 160#define IWN_APMG_CLK_CTRL 0x3000 161#define IWN_APMG_CLK_EN 0x3004 162#define IWN_APMG_CLK_DIS 0x3008 163#define IWN_APMG_PS 0x300c 164#define IWN_APMG_DIGITAL_SVR 0x3058 165#define IWN_APMG_ANALOG_SVR 0x306c 166#define IWN_APMG_PCI_STT 0x3010 167#define IWN_BSM_WR_CTRL 0x3400 168#define IWN_BSM_WR_MEM_SRC 0x3404 169#define IWN_BSM_WR_MEM_DST 0x3408 170#define IWN_BSM_WR_DWCOUNT 0x340c 171#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 172#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 173#define IWN_BSM_DRAM_DATA_ADDR 0x3498 174#define IWN_BSM_DRAM_DATA_SIZE 0x349c 175#define IWN_BSM_SRAM_BASE 0x3800 176 177/* Possible flags for register IWN_HW_IF_CONFIG. */ 178#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 179#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 180#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 181#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 182#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 183#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 184#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 185#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 186 187/* Possible values for register IWN_INT_PERIODIC. */ 188#define IWN_INT_PERIODIC_DIS 0x00 189#define IWN_INT_PERIODIC_ENA 0xff 190 191/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 192#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 193 194/* Possible values for IWN_BSM_WR_MEM_DST. */ 195#define IWN_FW_TEXT_BASE 0x00000000 196#define IWN_FW_DATA_BASE 0x00800000 197 198/* Possible flags for register IWN_RESET. */ 199#define IWN_RESET_NEVO (1 << 0) 200#define IWN_RESET_SW (1 << 7) 201#define IWN_RESET_MASTER_DISABLED (1 << 8) 202#define IWN_RESET_STOP_MASTER (1 << 9) 203#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 204 205/* Possible flags for register IWN_GP_CNTRL. */ 206#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 207#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 208#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 209#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 210#define IWN_GP_CNTRL_SLEEP (1 << 4) 211#define IWN_GP_CNTRL_RFKILL (1 << 27) 212 213/* Possible flags for register IWN_GIO_CHICKEN. */ 214#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 215#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 216 217/* Possible flags for register IWN_GIO. */ 218#define IWN_GIO_L0S_ENA (1 << 1) 219 220/* Possible flags for register IWN_GP_DRIVER. */ 221#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 224#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 225#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 226#define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 227#define IWN_GP_DRIVER_NONE 0 228 229/* Possible flags for register IWN_UCODE_GP1_CLR. */ 230#define IWN_UCODE_GP1_RFKILL (1 << 1) 231#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233#define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 234 235/* Possible flags/values for register IWN_LED. */ 236#define IWN_LED_BSM_CTRL (1 << 5) 237#define IWN_LED_OFF 0x00000038 238#define IWN_LED_ON 0x00000078 239 240#define IWN_MAX_BLINK_TBL 10 241#define IWN_LED_STATIC_ON 0 242#define IWN_LED_STATIC_OFF 1 243#define IWN_LED_SLOW_BLINK 2 244#define IWN_LED_INT_BLINK 3 245#define IWN_LED_UNIT 0x1388 /* 5 ms */ 246 247static const struct { 248 uint16_t tpt; /* Mb/s */ 249 uint8_t on_time; 250 uint8_t off_time; 251} blink_tbl[] = 252{ 253 {300, 5, 5}, 254 {200, 8, 8}, 255 {100, 11, 11}, 256 {70, 13, 13}, 257 {50, 15, 15}, 258 {20, 17, 17}, 259 {10, 19, 19}, 260 {5, 22, 22}, 261 {1, 26, 26}, 262 {0, 33, 33}, 263 /* SOLID_ON */ 264}; 265 266/* Possible flags for register IWN_DRAM_INT_TBL. */ 267#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 268#define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 269 270/* Possible values for register IWN_ANA_PLL. */ 271#define IWN_ANA_PLL_INIT 0x00880300 272 273/* Possible flags for register IWN_FH_RX_STATUS. */ 274#define IWN_FH_RX_STATUS_IDLE (1 << 24) 275 276/* Possible flags for register IWN_BSM_WR_CTRL. */ 277#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 278#define IWN_BSM_WR_CTRL_START (1U << 31) 279 280/* Possible flags for register IWN_INT. */ 281#define IWN_INT_ALIVE (1 << 0) 282#define IWN_INT_WAKEUP (1 << 1) 283#define IWN_INT_SW_RX (1 << 3) 284#define IWN_INT_CT_REACHED (1 << 6) 285#define IWN_INT_RF_TOGGLED (1 << 7) 286#define IWN_INT_SW_ERR (1 << 25) 287#define IWN_INT_SCHED (1 << 26) 288#define IWN_INT_FH_TX (1 << 27) 289#define IWN_INT_RX_PERIODIC (1 << 28) 290#define IWN_INT_HW_ERR (1 << 29) 291#define IWN_INT_FH_RX (1U << 31) 292 293/* Shortcut. */ 294#define IWN_INT_MASK_DEF \ 295 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 296 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 297 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 298 299/* Possible flags for register IWN_FH_INT. */ 300#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 301#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 302#define IWN_FH_INT_HI_PRIOR (1 << 30) 303/* Shortcuts for the above. */ 304#define IWN_FH_INT_TX \ 305 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 306#define IWN_FH_INT_RX \ 307 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 308 309/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 310#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 311#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 312#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 313 314/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 315#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 316#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 317#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 318 319/* Possible flags for register IWN_FH_TX_CHICKEN. */ 320#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 321 322/* Possible flags for register IWN_FH_TX_STATUS. */ 323#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 324 325/* Possible flags for register IWN_FH_RX_CONFIG. */ 326#define IWN_FH_RX_CONFIG_ENA (1U << 31) 327#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 328#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 329#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 330#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 331#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 332#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 333 334/* Possible flags for register IWN_FH_TX_CONFIG. */ 335#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 336#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 337 338/* Possible flags for register IWN_EEPROM. */ 339#define IWN_EEPROM_READ_VALID (1 << 0) 340#define IWN_EEPROM_CMD (1 << 1) 341 342/* Possible flags for register IWN_EEPROM_GP. */ 343#define IWN_EEPROM_GP_IF_OWNER 0x00000180 344 345/* Possible flags for register IWN_OTP_GP. */ 346#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 347#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 348#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 349#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 350 351/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 352#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 353#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 354#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 355#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 356#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 357#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 358#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 359 360/* Possible flags for registers IWN_APMG_CLK_*. */ 361#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 362#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 363 364/* Possible flags for register IWN_APMG_PS. */ 365#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 366#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 367#define IWN_APMG_PS_PWR_SRC_VMAIN 0 368#define IWN_APMG_PS_PWR_SRC_VAUX 2 369#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 370#define IWN_APMG_PS_RESET_REQ (1 << 26) 371 372/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 373#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 374#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 375 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 376#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 377 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 378 379/* Possible flags for IWN_APMG_PCI_STT. */ 380#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 381 382/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 383#define IWN_FW_UPDATED (1U << 31) 384 385#define IWN_SCHED_WINSZ 64 386#define IWN_SCHED_LIMIT 64 387#define IWN4965_SCHED_COUNT 512 388#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 389#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 390#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 391 392struct iwn_tx_desc { 393 uint8_t reserved1[3]; 394 uint8_t nsegs; 395 struct { 396 uint32_t addr; 397 uint16_t len; 398 } __packed segs[IWN_MAX_SCATTER]; 399 /* Pad to 128 bytes. */ 400 uint32_t reserved2; 401} __packed; 402 403struct iwn_rx_status { 404 uint16_t closed_count; 405 uint16_t closed_rx_count; 406 uint16_t finished_count; 407 uint16_t finished_rx_count; 408 uint32_t reserved[2]; 409} __packed; 410 411struct iwn_rx_desc { 412 /* 413 * The first 4 bytes of the RX frame header contain both the RX frame 414 * size and some flags. 415 * Bit fields: 416 * 31: flag flush RB request 417 * 30: flag ignore TC (terminal counter) request 418 * 29: flag fast IRQ request 419 * 28-14: Reserved 420 * 13-00: RX frame size 421 */ 422 uint32_t len; 423 uint8_t type; 424#define IWN_UC_READY 1 425#define IWN_ADD_NODE_DONE 24 426#define IWN_TX_DONE 28 427#define IWN_REPLY_LED_CMD 72 428#define IWN5000_CALIBRATION_RESULT 102 429#define IWN5000_CALIBRATION_DONE 103 430#define IWN_START_SCAN 130 431#define IWN_NOTIF_SCAN_RESULT 131 432#define IWN_STOP_SCAN 132 433#define IWN_RX_STATISTICS 156 434#define IWN_BEACON_STATISTICS 157 435#define IWN_STATE_CHANGED 161 436#define IWN_BEACON_MISSED 162 437#define IWN_RX_PHY 192 438#define IWN_MPDU_RX_DONE 193 439#define IWN_RX_DONE 195 440#define IWN_RX_COMPRESSED_BA 197 441 442 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 443 uint8_t idx; /* position within TX queue */ 444 uint8_t qid; 445 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 446 * or uCode-originated notification 447 */ 448} __packed; 449 450#define IWN_RX_DESC_QID_MSK 0x1F 451#define IWN_UNSOLICITED_RX_NOTIF 0x80 452 453/* CARD_STATE_NOTIFICATION */ 454#define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 455#define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 456#define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 457#define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 458 459/* Possible RX status flags. */ 460#define IWN_RX_NO_CRC_ERR (1 << 0) 461#define IWN_RX_NO_OVFL_ERR (1 << 1) 462/* Shortcut for the above. */ 463#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 464#define IWN_RX_MPDU_MIC_OK (1 << 6) 465#define IWN_RX_CIPHER_MASK (7 << 8) 466#define IWN_RX_CIPHER_CCMP (2 << 8) 467#define IWN_RX_MPDU_DEC (1 << 11) 468#define IWN_RX_DECRYPT_MASK (3 << 11) 469#define IWN_RX_DECRYPT_OK (3 << 11) 470 471struct iwn_tx_cmd { 472 uint8_t code; 473#define IWN_CMD_RXON 16 474#define IWN_CMD_RXON_ASSOC 17 475#define IWN_CMD_EDCA_PARAMS 19 476#define IWN_CMD_TIMING 20 477#define IWN_CMD_ADD_NODE 24 478#define IWN_CMD_TX_DATA 28 479#define IWN_CMD_LINK_QUALITY 78 480#define IWN_CMD_SET_LED 72 481#define IWN5000_CMD_WIMAX_COEX 90 482#define IWN_TEMP_NOTIFICATION 98 483#define IWN5000_CMD_CALIB_CONFIG 101 484#define IWN5000_CMD_CALIB_RESULT 102 485#define IWN5000_CMD_CALIB_COMPLETE 103 486#define IWN_CMD_SET_POWER_MODE 119 487#define IWN_CMD_SCAN 128 488#define IWN_CMD_SCAN_RESULTS 131 489#define IWN_CMD_TXPOWER_DBM 149 490#define IWN_CMD_TXPOWER 151 491#define IWN5000_CMD_TX_ANT_CONFIG 152 492#define IWN_CMD_TXPOWER_DBM_V1 152 493#define IWN_CMD_BT_COEX 155 494#define IWN_CMD_GET_STATISTICS 156 495#define IWN_CMD_SET_CRITICAL_TEMP 164 496#define IWN_CMD_SET_SENSITIVITY 168 497#define IWN_CMD_PHY_CALIB 176 498#define IWN_CMD_BT_COEX_PRIOTABLE 204 499#define IWN_CMD_BT_COEX_PROT 205 500#define IWN_CMD_BT_COEX_NOTIF 206 501/* PAN commands */ 502#define IWN_CMD_WIPAN_PARAMS 0xb2 503#define IWN_CMD_WIPAN_RXON 0xb3 504#define IWN_CMD_WIPAN_RXON_TIMING 0xb4 505#define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 506#define IWN_CMD_WIPAN_QOS_PARAM 0xb7 507#define IWN_CMD_WIPAN_WEPKEY 0xb8 508#define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 509#define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 510#define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 511 512 uint8_t flags; 513 uint8_t idx; 514 uint8_t qid; 515 uint8_t data[136]; 516} __packed; 517 518/* 519 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 520 * all devices identical. 521 * 522 * This command triggers an immediate response containing uCode statistics. 523 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 524 * 525 * If the CLEAR_STATS configuration flag is set, uCode will clear its 526 * internal copy of the statistics (counters) after issuing the response. 527 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 528 * 529 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 530 * IWN_BEACON_STATISTICS after received beacons. This flag 531 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 532 */ 533struct iwn_statistics_cmd { 534 uint32_t configuration_flags; 535#define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 536#define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 537} __packed; 538 539/* Antenna flags, used in various commands. */ 540#define IWN_ANT_A (1 << 0) 541#define IWN_ANT_B (1 << 1) 542#define IWN_ANT_C (1 << 2) 543/* Shortcuts. */ 544#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 545#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 546#define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 547#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 548 549/* Structure for command IWN_CMD_RXON. */ 550struct iwn_rxon { 551 uint8_t myaddr[IEEE80211_ADDR_LEN]; 552 uint16_t reserved1; 553 uint8_t bssid[IEEE80211_ADDR_LEN]; 554 uint16_t reserved2; 555 uint8_t wlap[IEEE80211_ADDR_LEN]; 556 uint16_t reserved3; 557 uint8_t mode; 558#define IWN_MODE_HOSTAP 1 559#define IWN_MODE_STA 3 560#define IWN_MODE_IBSS 4 561#define IWN_MODE_MONITOR 6 562#define IWN_MODE_2STA 8 563#define IWN_MODE_P2P 9 564 565 uint8_t air; 566 uint16_t rxchain; 567#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 568#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 569#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 570#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 571#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 572#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 573#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 574 575 uint8_t ofdm_mask; 576 uint8_t cck_mask; 577 uint16_t associd; 578 uint32_t flags; 579#define IWN_RXON_24GHZ (1 << 0) 580#define IWN_RXON_CCK (1 << 1) 581#define IWN_RXON_AUTO (1 << 2) 582#define IWN_RXON_SHSLOT (1 << 4) 583#define IWN_RXON_SHPREAMBLE (1 << 5) 584#define IWN_RXON_NODIVERSITY (1 << 7) 585#define IWN_RXON_ANTENNA_A (1 << 8) 586#define IWN_RXON_ANTENNA_B (1 << 9) 587#define IWN_RXON_TSF (1 << 15) 588#define IWN_RXON_HT_HT40MINUS (1 << 22) 589 590#define IWN_RXON_HT_PROTMODE(x) (x << 23) 591 592/* 0=legacy, 1=pure40, 2=mixed */ 593#define IWN_RXON_HT_MODEPURE40 (1 << 25) 594#define IWN_RXON_HT_MODEMIXED (2 << 25) 595 596#define IWN_RXON_CTS_TO_SELF (1 << 30) 597 598 uint32_t filter; 599#define IWN_FILTER_PROMISC (1 << 0) 600#define IWN_FILTER_CTL (1 << 1) 601#define IWN_FILTER_MULTICAST (1 << 2) 602#define IWN_FILTER_NODECRYPT (1 << 3) 603#define IWN_FILTER_BSS (1 << 5) 604#define IWN_FILTER_BEACON (1 << 6) 605 606 uint8_t chan; 607 uint8_t reserved4; 608 uint8_t ht_single_mask; 609 uint8_t ht_dual_mask; 610 /* The following fields are for >=5000 Series only. */ 611 uint8_t ht_triple_mask; 612 uint8_t reserved5; 613 uint16_t acquisition; 614 uint16_t reserved6; 615} __packed; 616 617#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 618#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 619 620/* Structure for command IWN_CMD_RXON_ASSOC (4965AGN only.) */ 621struct iwn4965_rxon_assoc { 622 uint32_t flags; 623 uint32_t filter; 624 uint8_t ofdm_mask; 625 uint8_t cck_mask; 626 uint8_t ht_single_mask; 627 uint8_t ht_dual_mask; 628 uint16_t rxchain; 629 uint16_t reserved; 630} __packed; 631 632/* Structure for command IWN_CMD_RXON_ASSOC (5000 Series only.) */ 633struct iwn5000_rxon_assoc { 634 uint32_t flags; 635 uint32_t filter; 636 uint8_t ofdm_mask; 637 uint8_t cck_mask; 638 uint16_t reserved1; 639 uint8_t ht_single_mask; 640 uint8_t ht_dual_mask; 641 uint8_t ht_triple_mask; 642 uint8_t reserved2; 643 uint16_t rxchain; 644 uint16_t acquisition; 645 uint32_t reserved3; 646} __packed; 647 648/* Structure for command IWN_CMD_ASSOCIATE. */ 649struct iwn_assoc { 650 uint32_t flags; 651 uint32_t filter; 652 uint8_t ofdm_mask; 653 uint8_t cck_mask; 654 uint16_t reserved; 655} __packed; 656 657/* Structure for command IWN_CMD_EDCA_PARAMS. */ 658struct iwn_edca_params { 659 uint32_t flags; 660#define IWN_EDCA_UPDATE (1 << 0) 661#define IWN_EDCA_TXOP (1 << 4) 662 663 struct { 664 uint16_t cwmin; 665 uint16_t cwmax; 666 uint8_t aifsn; 667 uint8_t reserved; 668 uint16_t txoplimit; 669 } __packed ac[WME_NUM_AC]; 670} __packed; 671 672/* Structure for command IWN_CMD_TIMING. */ 673struct iwn_cmd_timing { 674 uint64_t tstamp; 675 uint16_t bintval; 676 uint16_t atim; 677 uint32_t binitval; 678 uint16_t lintval; 679 uint8_t dtim_period; 680 uint8_t delta_cp_bss_tbtts; 681} __packed; 682 683/* Structure for command IWN_CMD_ADD_NODE. */ 684struct iwn_node_info { 685 uint8_t control; 686#define IWN_NODE_UPDATE (1 << 0) 687 688 uint8_t reserved1[3]; 689 690 uint8_t macaddr[IEEE80211_ADDR_LEN]; 691 uint16_t reserved2; 692 uint8_t id; 693#define IWN_ID_BSS 0 694#define IWN_STA_ID 1 695 696#define IWN_PAN_ID_BCAST 14 697#define IWN5000_ID_BROADCAST 15 698#define IWN4965_ID_BROADCAST 31 699 700#define IWN_ID_UNDEFINED (uint8_t)-1 701 702 uint8_t flags; 703#define IWN_FLAG_SET_KEY (1 << 0) 704#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 705#define IWN_FLAG_SET_TXRATE (1 << 2) 706#define IWN_FLAG_SET_ADDBA (1 << 3) 707#define IWN_FLAG_SET_DELBA (1 << 4) 708 709 uint16_t reserved3; 710 uint16_t kflags; 711#define IWN_KFLAG_CCMP (1 << 1) 712#define IWN_KFLAG_MAP (1 << 3) 713#define IWN_KFLAG_KID(kid) ((kid) << 8) 714#define IWN_KFLAG_INVALID (1 << 11) 715#define IWN_KFLAG_GROUP (1 << 14) 716 717 uint8_t tsc2; /* TKIP TSC2 */ 718 uint8_t reserved4; 719 uint16_t ttak[5]; 720 uint8_t kid; 721 uint8_t reserved5; 722 uint8_t key[16]; 723 /* The following 3 fields are for 5000 Series only. */ 724 uint64_t tsc; 725 uint8_t rxmic[8]; 726 uint8_t txmic[8]; 727 728 uint32_t htflags; 729#define IWN_SMPS_MIMO_PROT (1 << 17) 730#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 731#define IWN_NODE_HT40 (1 << 21) 732#define IWN_SMPS_MIMO_DIS (1 << 22) 733#define IWN_AMDPU_DENSITY(x) ((x) << 23) 734 735 uint32_t mask; 736 uint16_t disable_tid; 737 uint16_t reserved6; 738 uint8_t addba_tid; 739 uint8_t delba_tid; 740 uint16_t addba_ssn; 741 uint32_t reserved7; 742} __packed; 743 744struct iwn4965_node_info { 745 uint8_t control; 746 uint8_t reserved1[3]; 747 uint8_t macaddr[IEEE80211_ADDR_LEN]; 748 uint16_t reserved2; 749 uint8_t id; 750 uint8_t flags; 751 uint16_t reserved3; 752 uint16_t kflags; 753 uint8_t tsc2; /* TKIP TSC2 */ 754 uint8_t reserved4; 755 uint16_t ttak[5]; 756 uint8_t kid; 757 uint8_t reserved5; 758 uint8_t key[16]; 759 uint32_t htflags; 760 uint32_t mask; 761 uint16_t disable_tid; 762 uint16_t reserved6; 763 uint8_t addba_tid; 764 uint8_t delba_tid; 765 uint16_t addba_ssn; 766 uint32_t reserved7; 767} __packed; 768 769#define IWN_RFLAG_RATE 0xff 770#define IWN_RFLAG_RATE_MCS 0x1f 771#define IWN_RFLAG_HT40_DUP 0x20 772 773#define IWN_RFLAG_MCS (1 << 8) 774#define IWN_RFLAG_CCK (1 << 9) 775#define IWN_RFLAG_GREENFIELD (1 << 10) 776#define IWN_RFLAG_HT40 (1 << 11) 777#define IWN_RFLAG_DUPLICATE (1 << 12) 778#define IWN_RFLAG_SGI (1 << 13) 779#define IWN_RFLAG_ANT(x) ((x) << 14) 780 781/* Structure for command IWN_CMD_TX_DATA. */ 782struct iwn_cmd_data { 783 uint16_t len; 784 uint16_t lnext; 785 uint32_t flags; 786#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 787#define IWN_TX_NEED_RTS (1 << 1) 788#define IWN_TX_NEED_CTS (1 << 2) 789#define IWN_TX_NEED_ACK (1 << 3) 790#define IWN_TX_LINKQ (1 << 4) 791#define IWN_TX_IMM_BA (1 << 6) 792#define IWN_TX_FULL_TXOP (1 << 7) 793#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 794#define IWN_TX_AUTO_SEQ (1 << 13) 795#define IWN_TX_MORE_FRAG (1 << 14) 796#define IWN_TX_INSERT_TSTAMP (1 << 16) 797#define IWN_TX_NEED_PADDING (1 << 20) 798 799 uint32_t scratch; 800 uint32_t rate; 801 802 uint8_t id; 803 uint8_t security; 804#define IWN_CIPHER_WEP40 1 805#define IWN_CIPHER_CCMP 2 806#define IWN_CIPHER_TKIP 3 807#define IWN_CIPHER_WEP104 9 808 809 uint8_t linkq; 810 uint8_t reserved2; 811 uint8_t key[16]; 812 uint16_t fnext; 813 uint16_t reserved3; 814 uint32_t lifetime; 815#define IWN_LIFETIME_INFINITE 0xffffffff 816 817 uint32_t loaddr; 818 uint8_t hiaddr; 819 uint8_t rts_ntries; 820 uint8_t data_ntries; 821 uint8_t tid; 822 uint16_t timeout; 823 uint16_t txop; 824} __packed; 825 826/* Structure for command IWN_CMD_LINK_QUALITY. */ 827#define IWN_MAX_TX_RETRIES 16 828struct iwn_cmd_link_quality { 829 uint8_t id; 830 uint8_t reserved1; 831 uint16_t ctl; 832 uint8_t flags; 833 uint8_t mimo; 834 uint8_t antmsk_1stream; 835 uint8_t antmsk_2stream; 836 uint8_t ridx[WME_NUM_AC]; 837 uint16_t ampdu_limit; 838 uint8_t ampdu_threshold; 839 uint8_t ampdu_max; 840 uint32_t reserved2; 841 uint32_t retry[IWN_MAX_TX_RETRIES]; 842 uint32_t reserved3; 843} __packed; 844 845/* Structure for command IWN_CMD_SET_LED. */ 846struct iwn_cmd_led { 847 uint32_t unit; /* multiplier (in usecs) */ 848 uint8_t which; 849#define IWN_LED_ACTIVITY 1 850#define IWN_LED_LINK 2 851 852 uint8_t off; 853 uint8_t on; 854 uint8_t reserved; 855} __packed; 856 857/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 858struct iwn5000_wimax_coex { 859 uint32_t flags; 860#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 861#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 862#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 863#define IWN_WIMAX_COEX_ENABLE (1 << 7) 864 865 struct iwn5000_wimax_event { 866 uint8_t request; 867 uint8_t window; 868 uint8_t reserved; 869 uint8_t flags; 870 } __packed events[16]; 871} __packed; 872 873/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 874struct iwn5000_calib_elem { 875 uint32_t enable; 876 uint32_t start; 877#define IWN5000_CALIB_DC (1 << 1) 878 879 uint32_t send; 880 uint32_t apply; 881 uint32_t reserved; 882} __packed; 883 884struct iwn5000_calib_status { 885 struct iwn5000_calib_elem once; 886 struct iwn5000_calib_elem perd; 887 uint32_t flags; 888} __packed; 889 890struct iwn5000_calib_config { 891 struct iwn5000_calib_status ucode; 892 struct iwn5000_calib_status driver; 893 uint32_t reserved; 894} __packed; 895 896/* Structure for command IWN_CMD_SET_POWER_MODE. */ 897struct iwn_pmgt_cmd { 898 uint16_t flags; 899#define IWN_PS_ALLOW_SLEEP (1 << 0) 900#define IWN_PS_NOTIFY (1 << 1) 901#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 902#define IWN_PS_PCI_PMGT (1 << 3) 903#define IWN_PS_FAST_PD (1 << 4) 904#define IWN_PS_BEACON_FILTERING (1 << 5) 905#define IWN_PS_SHADOW_REG (1 << 6) 906#define IWN_PS_CT_KILL (1 << 7) 907#define IWN_PS_BT_SCD (1 << 8) 908#define IWN_PS_ADVANCED_PM (1 << 9) 909 910 uint8_t keepalive; 911 uint8_t debug; 912 uint32_t rxtimeout; 913 uint32_t txtimeout; 914 uint32_t intval[5]; 915 uint32_t beacons; 916} __packed; 917 918/* Structures for command IWN_CMD_SCAN. */ 919struct iwn_scan_essid { 920 uint8_t id; 921 uint8_t len; 922 uint8_t data[IEEE80211_NWID_LEN]; 923} __packed; 924 925struct iwn_scan_hdr { 926 uint16_t len; 927 uint8_t scan_flags; 928 uint8_t nchan; 929 uint16_t quiet_time; 930 uint16_t quiet_threshold; 931 uint16_t crc_threshold; 932 uint16_t rxchain; 933 uint32_t max_svc; /* background scans */ 934 uint32_t pause_svc; /* background scans */ 935 uint32_t flags; 936 uint32_t filter; 937 938 /* Followed by a struct iwn_cmd_data. */ 939 /* Followed by an array of 20 structs iwn_scan_essid. */ 940 /* Followed by probe request body. */ 941 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 942} __packed; 943 944struct iwn_scan_chan { 945 uint32_t flags; 946#define IWN_CHAN_PASSIVE (0 << 0) 947#define IWN_CHAN_ACTIVE (1 << 0) 948#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 949 950 uint16_t chan; 951 uint8_t rf_gain; 952 uint8_t dsp_gain; 953 uint16_t active; /* msecs */ 954 uint16_t passive; /* msecs */ 955} __packed; 956 957#define IWN_SCAN_CRC_TH_DISABLED 0 958#define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 959#define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 960 961/* Maximum size of a scan command. */ 962#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 963 964/* 965 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 966 * sending probe req. This should be set long enough to hear probe responses 967 * from more than one AP. 968 */ 969#define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 970#define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 971#define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 972#define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 973 974/* 975 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 976 * Must be set longer than active dwell time. 977 * For the most reliable scan, set > AP beacon interval (typically 100msec). 978 */ 979#define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 980#define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 981#define IWN_PASSIVE_DWELL_BASE (100) 982#define IWN_CHANNEL_TUNE_TIME (5) 983 984#define IWN_SCAN_CHAN_TIMEOUT 2 985#define IWN_MAX_SCAN_CHANNEL 50 986 987/* 988 * If active scanning is requested but a certain channel is 989 * marked passive, we can do active scanning if we detect 990 * transmissions. 991 * 992 * There is an issue with some firmware versions that triggers 993 * a sysassert on a "good CRC threshold" of zero (== disabled), 994 * on a radar channel even though this means that we should NOT 995 * send probes. 996 * 997 * The "good CRC threshold" is the number of frames that we 998 * need to receive during our dwell time on a channel before 999 * sending out probes -- setting this to a huge value will 1000 * mean we never reach it, but at the same time work around 1001 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 1002 * here instead of IWL_GOOD_CRC_TH_DISABLED. 1003 * 1004 * This was fixed in later versions along with some other 1005 * scan changes, and the threshold behaves as a flag in those 1006 * versions. 1007 */ 1008#define IWN_GOOD_CRC_TH_DISABLED 0 1009#define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 1010#define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 1011 1012/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 1013#define IWN_RIDX_MAX 32 1014struct iwn4965_cmd_txpower { 1015 uint8_t band; 1016 uint8_t reserved1; 1017 uint8_t chan; 1018 uint8_t reserved2; 1019 struct { 1020 uint8_t rf_gain[2]; 1021 uint8_t dsp_gain[2]; 1022 } __packed power[IWN_RIDX_MAX + 1]; 1023} __packed; 1024 1025/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 1026struct iwn5000_cmd_txpower { 1027 int8_t global_limit; /* in half-dBm */ 1028#define IWN5000_TXPOWER_AUTO 0x7f 1029#define IWN5000_TXPOWER_MAX_DBM 16 1030 1031 uint8_t flags; 1032#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 1033 1034 int8_t srv_limit; /* in half-dBm */ 1035 uint8_t reserved; 1036} __packed; 1037 1038/* Structures for command IWN_CMD_BLUETOOTH. */ 1039struct iwn_bluetooth { 1040 uint8_t flags; 1041#define IWN_BT_COEX_CHAN_ANN (1 << 0) 1042#define IWN_BT_COEX_BT_PRIO (1 << 1) 1043#define IWN_BT_COEX_2_WIRE (1 << 2) 1044 1045 uint8_t lead_time; 1046#define IWN_BT_LEAD_TIME_DEF 30 1047 1048 uint8_t max_kill; 1049#define IWN_BT_MAX_KILL_DEF 5 1050 1051 uint8_t reserved; 1052 uint32_t kill_ack; 1053 uint32_t kill_cts; 1054} __packed; 1055 1056struct iwn6000_btcoex_config { 1057 uint8_t flags; 1058#define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 1059#define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 1060#define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 1061#define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 1062#define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 1063#define IWN_BT_FLAG_COEX6000_MODE_3W 2 1064#define IWN_BT_FLAG_COEX6000_MODE_4W 3 1065 1066#define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 1067#define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 1068 uint8_t lead_time; 1069 uint8_t max_kill; 1070 uint8_t bt3_t7_timer; 1071 uint32_t kill_ack; 1072 uint32_t kill_cts; 1073 uint8_t sample_time; 1074 uint8_t bt3_t2_timer; 1075 uint16_t bt4_reaction; 1076 uint32_t lookup_table[12]; 1077 uint16_t bt4_decision; 1078 uint16_t valid; 1079 uint8_t prio_boost; 1080 uint8_t tx_prio_boost; 1081 uint16_t rx_prio_boost; 1082} __packed; 1083 1084/* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1085struct iwn2000_btcoex_config { 1086 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1087 uint8_t lead_time; 1088 uint8_t max_kill; 1089 uint8_t bt3_t7_timer; 1090 uint32_t kill_ack; 1091 uint32_t kill_cts; 1092 uint8_t sample_time; 1093 uint8_t bt3_t2_timer; 1094 uint16_t bt4_reaction; 1095 uint32_t lookup_table[12]; 1096 uint16_t bt4_decision; 1097 uint16_t valid; 1098 1099 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1100 uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1101 1102 uint8_t tx_prio_boost; 1103 uint16_t rx_prio_boost; 1104} __packed; 1105 1106struct iwn_btcoex_priotable { 1107 uint8_t calib_init1; 1108 uint8_t calib_init2; 1109 uint8_t calib_periodic_low1; 1110 uint8_t calib_periodic_low2; 1111 uint8_t calib_periodic_high1; 1112 uint8_t calib_periodic_high2; 1113 uint8_t dtim; 1114 uint8_t scan52; 1115 uint8_t scan24; 1116 uint8_t reserved[7]; 1117} __packed; 1118 1119struct iwn_btcoex_prot { 1120 uint8_t open; 1121 uint8_t type; 1122 uint8_t reserved[2]; 1123} __packed; 1124 1125/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1126struct iwn_critical_temp { 1127 uint32_t reserved; 1128 uint32_t tempM; 1129 uint32_t tempR; 1130/* degK <-> degC conversion macros. */ 1131#define IWN_CTOK(c) ((c) + 273) 1132#define IWN_KTOC(k) ((k) - 273) 1133#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1134} __packed; 1135 1136/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1137struct iwn_sensitivity_cmd { 1138 uint16_t which; 1139#define IWN_SENSITIVITY_DEFAULTTBL 0 1140#define IWN_SENSITIVITY_WORKTBL 1 1141 1142 uint16_t energy_cck; 1143 uint16_t energy_ofdm; 1144 uint16_t corr_ofdm_x1; 1145 uint16_t corr_ofdm_mrc_x1; 1146 uint16_t corr_cck_mrc_x4; 1147 uint16_t corr_ofdm_x4; 1148 uint16_t corr_ofdm_mrc_x4; 1149 uint16_t corr_barker; 1150 uint16_t corr_barker_mrc; 1151 uint16_t corr_cck_x4; 1152 uint16_t energy_ofdm_th; 1153} __packed; 1154 1155struct iwn_enhanced_sensitivity_cmd { 1156 uint16_t which; 1157 uint16_t energy_cck; 1158 uint16_t energy_ofdm; 1159 uint16_t corr_ofdm_x1; 1160 uint16_t corr_ofdm_mrc_x1; 1161 uint16_t corr_cck_mrc_x4; 1162 uint16_t corr_ofdm_x4; 1163 uint16_t corr_ofdm_mrc_x4; 1164 uint16_t corr_barker; 1165 uint16_t corr_barker_mrc; 1166 uint16_t corr_cck_x4; 1167 uint16_t energy_ofdm_th; 1168 /* "Enhanced" part. */ 1169 uint16_t ina_det_ofdm; 1170 uint16_t ina_det_cck; 1171 uint16_t corr_11_9_en; 1172 uint16_t ofdm_det_slope_mrc; 1173 uint16_t ofdm_det_icept_mrc; 1174 uint16_t ofdm_det_slope; 1175 uint16_t ofdm_det_icept; 1176 uint16_t cck_det_slope_mrc; 1177 uint16_t cck_det_icept_mrc; 1178 uint16_t cck_det_slope; 1179 uint16_t cck_det_icept; 1180 uint16_t reserved; 1181} __packed; 1182 1183/* 1184 * Define maximal number of calib result send to runtime firmware 1185 * PS: TEMP_OFFSET count for 2 (std and v2) 1186 */ 1187#define IWN5000_PHY_CALIB_MAX_RESULT 8 1188 1189/* Structures for command IWN_CMD_PHY_CALIB. */ 1190struct iwn_phy_calib { 1191 uint8_t code; 1192#define IWN4965_PHY_CALIB_DIFF_GAIN 7 1193#define IWN5000_PHY_CALIB_DC 8 1194#define IWN5000_PHY_CALIB_LO 9 1195#define IWN5000_PHY_CALIB_TX_IQ 11 1196#define IWN5000_PHY_CALIB_CRYSTAL 15 1197#define IWN5000_PHY_CALIB_BASE_BAND 16 1198#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1199#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1200 1201#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1202#define IWN5000_PHY_CALIB_NOISE_GAIN 19 1203 1204 uint8_t group; 1205 uint8_t ngroups; 1206 uint8_t isvalid; 1207} __packed; 1208 1209struct iwn5000_phy_calib_crystal { 1210 uint8_t code; 1211 uint8_t group; 1212 uint8_t ngroups; 1213 uint8_t isvalid; 1214 1215 uint8_t cap_pin[2]; 1216 uint8_t reserved[2]; 1217} __packed; 1218 1219struct iwn5000_phy_calib_temp_offset { 1220 uint8_t code; 1221 uint8_t group; 1222 uint8_t ngroups; 1223 uint8_t isvalid; 1224 int16_t offset; 1225#define IWN_DEFAULT_TEMP_OFFSET 2700 1226 1227 uint16_t reserved; 1228} __packed; 1229 1230struct iwn5000_phy_calib_temp_offsetv2 { 1231 uint8_t code; 1232 uint8_t group; 1233 uint8_t ngroups; 1234 uint8_t isvalid; 1235 int16_t offset_high; 1236 int16_t offset_low; 1237 int16_t burnt_voltage_ref; 1238 int16_t reserved; 1239} __packed; 1240 1241struct iwn_phy_calib_gain { 1242 uint8_t code; 1243 uint8_t group; 1244 uint8_t ngroups; 1245 uint8_t isvalid; 1246 1247 int8_t gain[3]; 1248 uint8_t reserved; 1249} __packed; 1250 1251/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1252struct iwn_spectrum_cmd { 1253 uint16_t len; 1254 uint8_t token; 1255 uint8_t id; 1256 uint8_t origin; 1257 uint8_t periodic; 1258 uint16_t timeout; 1259 uint32_t start; 1260 uint32_t reserved1; 1261 uint32_t flags; 1262 uint32_t filter; 1263 uint16_t nchan; 1264 uint16_t reserved2; 1265 struct { 1266 uint32_t duration; 1267 uint8_t chan; 1268 uint8_t type; 1269#define IWN_MEASUREMENT_BASIC (1 << 0) 1270#define IWN_MEASUREMENT_CCA (1 << 1) 1271#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1272#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1273#define IWN_MEASUREMENT_FRAME (1 << 4) 1274#define IWN_MEASUREMENT_IDLE (1 << 7) 1275 1276 uint16_t reserved; 1277 } __packed chan[10]; 1278} __packed; 1279 1280/* Structure for IWN_UC_READY notification. */ 1281#define IWN_NATTEN_GROUPS 5 1282struct iwn_ucode_info { 1283 uint8_t minor; 1284 uint8_t major; 1285 uint16_t reserved1; 1286 uint8_t revision[8]; 1287 uint8_t type; 1288 uint8_t subtype; 1289#define IWN_UCODE_RUNTIME 0 1290#define IWN_UCODE_INIT 9 1291 1292 uint16_t reserved2; 1293 uint32_t logptr; 1294 uint32_t errptr; 1295 uint32_t tstamp; 1296 uint32_t valid; 1297 1298 /* The following fields are for UCODE_INIT only. */ 1299 int32_t volt; 1300 struct { 1301 int32_t chan20MHz; 1302 int32_t chan40MHz; 1303 } __packed temp[4]; 1304 int32_t atten[IWN_NATTEN_GROUPS][2]; 1305} __packed; 1306 1307/* Structures for IWN_TX_DONE notification. */ 1308 1309/* 1310 * TX command response is sent after *agn* transmission attempts. 1311 * 1312 * both postpone and abort status are expected behavior from uCode. there is 1313 * no special operation required from driver; except for RFKILL_FLUSH, 1314 * which required tx flush host command to flush all the tx frames in queues 1315 */ 1316#define IWN_TX_STATUS_MSK 0x000000ff 1317#define IWN_TX_STATUS_DELAY_MSK 0x00000040 1318#define IWN_TX_STATUS_ABORT_MSK 0x00000080 1319#define IWN_TX_PACKET_MODE_MSK 0x0000ff00 1320#define IWN_TX_FIFO_NUMBER_MSK 0x00070000 1321#define IWN_TX_RESERVED 0x00780000 1322#define IWN_TX_POWER_PA_DETECT_MSK 0x7f800000 1323#define IWN_TX_ABORT_REQUIRED_MSK 0x80000000 1324 1325/* Success status */ 1326#define IWN_TX_STATUS_SUCCESS 0x01 1327#define IWN_TX_STATUS_DIRECT_DONE 0x02 1328 1329/* postpone TX */ 1330#define IWN_TX_STATUS_POSTPONE_DELAY 0x40 1331#define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41 1332#define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42 1333#define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 1334#define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44 1335 1336/* Failures */ 1337#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1338#define IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 1339#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1340#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1341#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1342#define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85 1343#define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 1344#define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 1345#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1346#define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89 1347#define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a 1348#define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */ 1349#define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 1350#define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d 1351#define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 1352#define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 1353#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1354#define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 1355 1356/* 1357 * TX command response for A-MPDU packet responses. 1358 * 1359 * The status response is different to the non A-MPDU responses. 1360 * In addition, the sequence number is treated as the sequence 1361 * number of the TX command, NOT the 802.11 sequence number! 1362 */ 1363#define IWN_AGG_TX_STATE_TRANSMITTED 0x00 1364#define IWN_AGG_TX_STATE_UNDERRUN_MSK 0x01 1365#define IWN_AGG_TX_STATE_FEW_BYTES_MSK 0x04 1366#define IWN_AGG_TX_STATE_ABORT_MSK 0x08 1367 1368#define IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK 0x10 1369#define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK 0x20 1370 1371#define IWN_AGG_TX_STATE_SCD_QUERY_MSK 0x80 1372 1373#define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100 1374 1375#define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff 1376#define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200 1377#define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400 1378 1379#define IWN_AGG_TX_STATUS_MSK 0x00000fff 1380#define IWN_AGG_TX_TRY_MSK 0x0000f000 1381#define IWN_AGG_TX_TRY_POS 12 1382#define IWN_AGG_TX_TRY_COUNT(status) \ 1383 (((status) & IWN_AGG_TX_TRY_MSK) >> IWN_AGG_TX_TRY_POS) 1384 1385#define IWN_AGG_TX_STATE_LAST_SENT_MSK \ 1386 (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \ 1387 IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK) 1388 1389#define IWN_AGG_TX_STATE_IGNORE_MASK \ 1390 (IWN_AGG_TX_STATE_FEW_BYTES_MSK | \ 1391 IWN_AGG_TX_STATE_ABORT_MSK) 1392 1393/* # tx attempts for first frame in aggregation */ 1394#define IWN_AGG_TX_STATE_TRY_CNT_POS 12 1395#define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000 1396 1397/* Command ID and sequence number of Tx command for this frame */ 1398#define IWN_AGG_TX_STATE_SEQ_NUM_POS 16 1399#define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 1400 1401struct iwn4965_tx_stat { 1402 uint8_t nframes; 1403 uint8_t btkillcnt; 1404 uint8_t rtsfailcnt; 1405 uint8_t ackfailcnt; 1406 uint32_t rate; 1407 uint16_t duration; 1408 uint16_t reserved; 1409 uint32_t power[2]; 1410 uint32_t status; 1411} __packed; 1412 1413struct iwn5000_tx_stat { 1414 uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1415 uint8_t btkillcnt; 1416 uint8_t rtsfailcnt; 1417 uint8_t ackfailcnt; 1418 uint32_t rate; 1419 uint16_t duration; 1420 uint16_t reserved; 1421 uint32_t power[2]; 1422 uint32_t info; 1423 uint16_t seq; 1424 uint16_t len; 1425 uint8_t tlc; 1426 uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1427 uint8_t fc[2]; 1428 uint16_t status; 1429 uint16_t sequence; 1430} __packed; 1431 1432/* Structure for IWN_BEACON_MISSED notification. */ 1433struct iwn_beacon_missed { 1434 uint32_t consecutive; 1435 uint32_t total; 1436 uint32_t expected; 1437 uint32_t received; 1438} __packed; 1439 1440/* Structure for IWN_MPDU_RX_DONE notification. */ 1441struct iwn_rx_mpdu { 1442 uint16_t len; 1443 uint16_t reserved; 1444} __packed; 1445 1446/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1447struct iwn4965_rx_phystat { 1448 uint16_t antenna; 1449 uint16_t agc; 1450 uint8_t rssi[6]; 1451} __packed; 1452 1453struct iwn5000_rx_phystat { 1454 uint32_t reserved1; 1455 uint32_t agc; 1456 uint16_t rssi[3]; 1457} __packed; 1458 1459struct iwn_rx_stat { 1460 uint8_t phy_len; 1461 uint8_t cfg_phy_len; 1462#define IWN_STAT_MAXLEN 20 1463 1464 uint8_t id; 1465 uint8_t reserved1; 1466 uint64_t tstamp; 1467 uint32_t beacon; 1468 uint16_t flags; 1469#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1470 1471 uint16_t chan; 1472 uint8_t phybuf[32]; 1473 uint32_t rate; 1474/* 1475 * rate bit fields 1476 * 1477 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1478 * 2-0: 0) 6 Mbps 1479 * 1) 12 Mbps 1480 * 2) 18 Mbps 1481 * 3) 24 Mbps 1482 * 4) 36 Mbps 1483 * 5) 48 Mbps 1484 * 6) 54 Mbps 1485 * 7) 60 Mbps 1486 * 1487 * 4-3: 0) Single stream (SISO) 1488 * 1) Dual stream (MIMO) 1489 * 2) Triple stream (MIMO) 1490 * 1491 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1492 * 1493 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1494 * 3-0: 0xD) 6 Mbps 1495 * 0xF) 9 Mbps 1496 * 0x5) 12 Mbps 1497 * 0x7) 18 Mbps 1498 * 0x9) 24 Mbps 1499 * 0xB) 36 Mbps 1500 * 0x1) 48 Mbps 1501 * 0x3) 54 Mbps 1502 * 1503 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1504 * 6-0: 10) 1 Mbps 1505 * 20) 2 Mbps 1506 * 55) 5.5 Mbps 1507 * 110) 11 Mbps 1508 * 1509 */ 1510 uint16_t len; 1511 uint16_t reserve3; 1512} __packed; 1513 1514#define IWN_RSSI_TO_DBM 44 1515 1516/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1517struct iwn_compressed_ba { 1518 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1519 uint16_t reserved; 1520 uint8_t id; 1521 uint8_t tid; 1522 uint16_t seq; 1523 uint64_t bitmap; 1524 uint16_t qid; 1525 uint16_t ssn; 1526 /* extra fields starting with iwn5000 */ 1527#if 0 1528 uint8_t txed; /* number of frames sent */ 1529 uint8_t txed_2_done; /* number of frames acked */ 1530 uint16_t reserved1; 1531#endif 1532} __packed; 1533 1534/* Structure for IWN_START_SCAN notification. */ 1535struct iwn_start_scan { 1536 uint64_t tstamp; 1537 uint32_t tbeacon; 1538 uint8_t chan; 1539 uint8_t band; 1540 uint16_t reserved; 1541 uint32_t status; 1542} __packed; 1543 1544/* Structure for IWN_STOP_SCAN notification. */ 1545struct iwn_stop_scan { 1546 uint8_t nchan; 1547 uint8_t status; 1548 uint8_t reserved; 1549 uint8_t chan; 1550 uint64_t tsf; 1551} __packed; 1552 1553/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1554struct iwn_spectrum_notif { 1555 uint8_t id; 1556 uint8_t token; 1557 uint8_t idx; 1558 uint8_t state; 1559#define IWN_MEASUREMENT_START 0 1560#define IWN_MEASUREMENT_STOP 1 1561 1562 uint32_t start; 1563 uint8_t band; 1564 uint8_t chan; 1565 uint8_t type; 1566 uint8_t reserved1; 1567 uint32_t cca_ofdm; 1568 uint32_t cca_cck; 1569 uint32_t cca_time; 1570 uint8_t basic; 1571 uint8_t reserved2[3]; 1572 uint32_t ofdm[8]; 1573 uint32_t cck[8]; 1574 uint32_t stop; 1575 uint32_t status; 1576#define IWN_MEASUREMENT_OK 0 1577#define IWN_MEASUREMENT_CONCURRENT 1 1578#define IWN_MEASUREMENT_CSA_CONFLICT 2 1579#define IWN_MEASUREMENT_TGH_CONFLICT 3 1580#define IWN_MEASUREMENT_STOPPED 6 1581#define IWN_MEASUREMENT_TIMEOUT 7 1582#define IWN_MEASUREMENT_FAILED 8 1583} __packed; 1584 1585/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1586struct iwn_rx_phy_stats { 1587 uint32_t ina; 1588 uint32_t fina; 1589 uint32_t bad_plcp; 1590 uint32_t bad_crc32; 1591 uint32_t overrun; 1592 uint32_t eoverrun; 1593 uint32_t good_crc32; 1594 uint32_t fa; 1595 uint32_t bad_fina_sync; 1596 uint32_t sfd_timeout; 1597 uint32_t fina_timeout; 1598 uint32_t no_rts_ack; 1599 uint32_t rxe_limit; 1600 uint32_t ack; 1601 uint32_t cts; 1602 uint32_t ba_resp; 1603 uint32_t dsp_kill; 1604 uint32_t bad_mh; 1605 uint32_t rssi_sum; 1606 uint32_t reserved; 1607} __packed; 1608 1609struct iwn_rx_general_stats { 1610 uint32_t bad_cts; 1611 uint32_t bad_ack; 1612 uint32_t not_bss; 1613 uint32_t filtered; 1614 uint32_t bad_chan; 1615 uint32_t beacons; 1616 uint32_t missed_beacons; 1617 uint32_t adc_saturated; /* time in 0.8us */ 1618 uint32_t ina_searched; /* time in 0.8us */ 1619 uint32_t noise[3]; 1620 uint32_t flags; 1621 uint32_t load; 1622 uint32_t fa; 1623 uint32_t rssi[3]; 1624 uint32_t energy[3]; 1625} __packed; 1626 1627struct iwn_rx_ht_phy_stats { 1628 uint32_t bad_plcp; 1629 uint32_t overrun; 1630 uint32_t eoverrun; 1631 uint32_t good_crc32; 1632 uint32_t bad_crc32; 1633 uint32_t bad_mh; 1634 uint32_t good_ampdu_crc32; 1635 uint32_t ampdu; 1636 uint32_t fragment; 1637 uint32_t unsupport_mcs; 1638} __packed; 1639 1640struct iwn_rx_stats { 1641 struct iwn_rx_phy_stats ofdm; 1642 struct iwn_rx_phy_stats cck; 1643 struct iwn_rx_general_stats general; 1644 struct iwn_rx_ht_phy_stats ht; 1645} __packed; 1646 1647struct iwn_rx_general_stats_bt { 1648 struct iwn_rx_general_stats common; 1649 /* additional stats for bt */ 1650 uint32_t num_bt_kills; 1651 uint32_t reserved[2]; 1652} __packed; 1653 1654struct iwn_rx_stats_bt { 1655 struct iwn_rx_phy_stats ofdm; 1656 struct iwn_rx_phy_stats cck; 1657 struct iwn_rx_general_stats_bt general_bt; 1658 struct iwn_rx_ht_phy_stats ht; 1659} __packed; 1660 1661struct iwn_tx_stats { 1662 uint32_t preamble; 1663 uint32_t rx_detected; 1664 uint32_t bt_defer; 1665 uint32_t bt_kill; 1666 uint32_t short_len; 1667 uint32_t cts_timeout; 1668 uint32_t ack_timeout; 1669 uint32_t exp_ack; 1670 uint32_t ack; 1671 uint32_t msdu; 1672 uint32_t burst_err1; 1673 uint32_t burst_err2; 1674 uint32_t cts_collision; 1675 uint32_t ack_collision; 1676 uint32_t ba_timeout; 1677 uint32_t ba_resched; 1678 uint32_t query_ampdu; 1679 uint32_t query; 1680 uint32_t query_ampdu_frag; 1681 uint32_t query_mismatch; 1682 uint32_t not_ready; 1683 uint32_t underrun; 1684 uint32_t bt_ht_kill; 1685 uint32_t rx_ba_resp; 1686 /* 1687 * 6000 series only - LSB=ant A, ant B, ant C, MSB=reserved 1688 * TX power on chain in 1/2 dBm. 1689 */ 1690 uint32_t tx_power; 1691 uint32_t reserved[1]; 1692} __packed; 1693 1694struct iwn_general_stats { 1695 uint32_t temp; /* radio temperature */ 1696 uint32_t temp_m; /* radio voltage */ 1697 uint32_t burst_check; 1698 uint32_t burst; 1699 uint32_t wait_for_silence_timeout_cnt; 1700 uint32_t reserved1[3]; 1701 uint32_t sleep; 1702 uint32_t slot_out; 1703 uint32_t slot_idle; 1704 uint32_t ttl_tstamp; 1705 uint32_t tx_ant_a; 1706 uint32_t tx_ant_b; 1707 uint32_t exec; 1708 uint32_t probe; 1709 uint32_t reserved2[2]; 1710 uint32_t rx_enabled; 1711 /* 1712 * This is the number of times we have to re-tune 1713 * in order to get out of bad PHY status. 1714 */ 1715 uint32_t num_of_sos_states; 1716} __packed; 1717 1718struct iwn_stats { 1719 uint32_t flags; 1720 struct iwn_rx_stats rx; 1721 struct iwn_tx_stats tx; 1722 struct iwn_general_stats general; 1723 uint32_t reserved1[2]; 1724} __packed; 1725 1726struct iwn_bt_activity_stats { 1727 /* Tx statistics */ 1728 uint32_t hi_priority_tx_req_cnt; 1729 uint32_t hi_priority_tx_denied_cnt; 1730 uint32_t lo_priority_tx_req_cnt; 1731 uint32_t lo_priority_tx_denied_cnt; 1732 /* Rx statistics */ 1733 uint32_t hi_priority_rx_req_cnt; 1734 uint32_t hi_priority_rx_denied_cnt; 1735 uint32_t lo_priority_rx_req_cnt; 1736 uint32_t lo_priority_rx_denied_cnt; 1737} __packed; 1738 1739struct iwn_stats_bt { 1740 uint32_t flags; 1741 struct iwn_rx_stats_bt rx_bt; 1742 struct iwn_tx_stats tx; 1743 struct iwn_general_stats general; 1744 struct iwn_bt_activity_stats activity; 1745 uint32_t reserved1[2]; 1746}; 1747 1748/* Firmware error dump. */ 1749struct iwn_fw_dump { 1750 uint32_t valid; 1751 uint32_t id; 1752 uint32_t pc; 1753 uint32_t branch_link[2]; 1754 uint32_t interrupt_link[2]; 1755 uint32_t error_data[2]; 1756 uint32_t src_line; 1757 uint32_t tsf; 1758 uint32_t time[2]; 1759} __packed; 1760 1761/* TLV firmware header. */ 1762struct iwn_fw_tlv_hdr { 1763 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1764 uint32_t signature; 1765#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1766 1767 uint8_t descr[64]; 1768 uint32_t rev; 1769#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1770 1771 uint32_t build; 1772 uint64_t altmask; 1773} __packed; 1774 1775/* TLV header. */ 1776struct iwn_fw_tlv { 1777 uint16_t type; 1778#define IWN_FW_TLV_MAIN_TEXT 1 1779#define IWN_FW_TLV_MAIN_DATA 2 1780#define IWN_FW_TLV_INIT_TEXT 3 1781#define IWN_FW_TLV_INIT_DATA 4 1782#define IWN_FW_TLV_BOOT_TEXT 5 1783#define IWN_FW_TLV_PBREQ_MAXLEN 6 1784#define IWN_FW_TLV_PAN 7 1785#define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1786#define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1787#define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1788#define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1789#define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1790#define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1791#define IWN_FW_TLV_ENH_SENS 14 1792#define IWN_FW_TLV_PHY_CALIB 15 1793#define IWN_FW_TLV_WOWLAN_INST 16 1794#define IWN_FW_TLV_WOWLAN_DATA 17 1795#define IWN_FW_TLV_FLAGS 18 1796 1797 uint16_t alt; 1798 uint32_t len; 1799} __packed; 1800 1801#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1802#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1803#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1804#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1805#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1806#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1807#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1808 1809/* 1810 * Microcode flags TLV (18.) 1811 */ 1812 1813/** 1814 * enum iwn_ucode_tlv_flag - ucode API flags 1815 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1816 * was a separate TLV but moved here to save space. 1817 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1818 * treats good CRC threshold as a boolean 1819 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1820 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1821 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1822 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1823 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1824 * offload profile config command. 1825 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1826 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1827 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1828 * (rather than two) IPv6 addresses 1829 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1830 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1831 * from the probe request template. 1832 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1833 * connection when going back to D0 1834 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1835 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1836 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1837 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1838 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1839 * containing CAM (Continuous Active Mode) indication. 1840 */ 1841enum iwn_ucode_tlv_flag { 1842 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1843 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1844 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1845 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1846 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1847 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1848 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1849 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1850 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1851 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1852 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1853 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1854 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1855 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1856 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1857 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1858 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1859 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1860 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1861}; 1862 1863/* 1864 * Offsets into EEPROM. 1865 */ 1866#define IWN_EEPROM_MAC 0x015 1867#define IWN_EEPROM_SKU_CAP 0x045 1868#define IWN_EEPROM_RFCFG 0x048 1869#define IWN4965_EEPROM_DOMAIN 0x060 1870#define IWN4965_EEPROM_BAND1 0x063 1871#define IWN5000_EEPROM_REG 0x066 1872#define IWN5000_EEPROM_CAL 0x067 1873#define IWN4965_EEPROM_BAND2 0x072 1874#define IWN4965_EEPROM_BAND3 0x080 1875#define IWN4965_EEPROM_BAND4 0x08d 1876#define IWN4965_EEPROM_BAND5 0x099 1877#define IWN4965_EEPROM_BAND6 0x0a0 1878#define IWN4965_EEPROM_BAND7 0x0a8 1879#define IWN4965_EEPROM_MAXPOW 0x0e8 1880#define IWN4965_EEPROM_VOLTAGE 0x0e9 1881#define IWN4965_EEPROM_BANDS 0x0ea 1882/* Indirect offsets. */ 1883#define IWN5000_EEPROM_NO_HT40 0x000 1884#define IWN5000_EEPROM_DOMAIN 0x001 1885#define IWN5000_EEPROM_BAND1 0x004 1886#define IWN5000_EEPROM_BAND2 0x013 1887#define IWN5000_EEPROM_BAND3 0x021 1888#define IWN5000_EEPROM_BAND4 0x02e 1889#define IWN5000_EEPROM_BAND5 0x03a 1890#define IWN5000_EEPROM_BAND6 0x041 1891#define IWN6000_EEPROM_BAND6 0x040 1892#define IWN5000_EEPROM_BAND7 0x049 1893#define IWN6000_EEPROM_ENHINFO 0x054 1894#define IWN5000_EEPROM_CRYSTAL 0x128 1895#define IWN5000_EEPROM_TEMP 0x12a 1896#define IWN5000_EEPROM_VOLT 0x12b 1897 1898/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1899#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1900#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1901#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1902 1903/* Possible flags for IWN_EEPROM_RFCFG. */ 1904#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1905#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1906#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1907#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1908#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1909 1910struct iwn_eeprom_chan { 1911 uint8_t flags; 1912#define IWN_EEPROM_CHAN_VALID (1 << 0) 1913#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1914#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1915#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1916 1917 int8_t maxpwr; 1918} __packed; 1919 1920struct iwn_eeprom_enhinfo { 1921 uint8_t flags; 1922#define IWN_ENHINFO_VALID 0x01 1923#define IWN_ENHINFO_5GHZ 0x02 1924#define IWN_ENHINFO_OFDM 0x04 1925#define IWN_ENHINFO_HT40 0x08 1926#define IWN_ENHINFO_HTAP 0x10 1927#define IWN_ENHINFO_RES1 0x20 1928#define IWN_ENHINFO_RES2 0x40 1929#define IWN_ENHINFO_COMMON 0x80 1930 1931 uint8_t chan; 1932 int8_t chain[3]; /* max power in half-dBm */ 1933 uint8_t reserved; 1934 int8_t mimo2; /* max power in half-dBm */ 1935 int8_t mimo3; /* max power in half-dBm */ 1936} __packed; 1937 1938struct iwn5000_eeprom_calib_hdr { 1939 uint8_t version; 1940 uint8_t pa_type; 1941 uint16_t volt; 1942} __packed; 1943 1944#define IWN_NSAMPLES 3 1945struct iwn4965_eeprom_chan_samples { 1946 uint8_t num; 1947 struct { 1948 uint8_t temp; 1949 uint8_t gain; 1950 uint8_t power; 1951 int8_t pa_det; 1952 } samples[2][IWN_NSAMPLES]; 1953} __packed; 1954 1955#define IWN_NBANDS 8 1956struct iwn4965_eeprom_band { 1957 uint8_t lo; /* low channel number */ 1958 uint8_t hi; /* high channel number */ 1959 struct iwn4965_eeprom_chan_samples chans[2]; 1960} __packed; 1961 1962/* 1963 * Offsets of channels descriptions in EEPROM. 1964 */ 1965static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1966 IWN4965_EEPROM_BAND1, 1967 IWN4965_EEPROM_BAND2, 1968 IWN4965_EEPROM_BAND3, 1969 IWN4965_EEPROM_BAND4, 1970 IWN4965_EEPROM_BAND5, 1971 IWN4965_EEPROM_BAND6, 1972 IWN4965_EEPROM_BAND7 1973}; 1974 1975static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1976 IWN5000_EEPROM_BAND1, 1977 IWN5000_EEPROM_BAND2, 1978 IWN5000_EEPROM_BAND3, 1979 IWN5000_EEPROM_BAND4, 1980 IWN5000_EEPROM_BAND5, 1981 IWN5000_EEPROM_BAND6, 1982 IWN5000_EEPROM_BAND7 1983}; 1984 1985static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1986 IWN5000_EEPROM_BAND1, 1987 IWN5000_EEPROM_BAND2, 1988 IWN5000_EEPROM_BAND3, 1989 IWN5000_EEPROM_BAND4, 1990 IWN5000_EEPROM_BAND5, 1991 IWN6000_EEPROM_BAND6, 1992 IWN5000_EEPROM_BAND7 1993}; 1994 1995static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1996 IWN5000_EEPROM_BAND1, 1997 IWN5000_EEPROM_BAND2, 1998 IWN5000_EEPROM_BAND3, 1999 IWN5000_EEPROM_BAND4, 2000 IWN5000_EEPROM_BAND5, 2001 IWN5000_EEPROM_BAND6, 2002 IWN5000_EEPROM_NO_HT40, 2003}; 2004 2005static const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = { 2006 IWN5000_EEPROM_BAND1, 2007 IWN5000_EEPROM_BAND2, 2008 IWN5000_EEPROM_BAND3, 2009 IWN5000_EEPROM_BAND4, 2010 IWN5000_EEPROM_BAND5, 2011 IWN6000_EEPROM_BAND6, 2012 IWN5000_EEPROM_BAND7 2013}; 2014 2015#define IWN_CHAN_BANDS_COUNT 7 2016#define IWN_MAX_CHAN_PER_BAND 14 2017static const struct iwn_chan_band { 2018 uint8_t nchan; 2019 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 2020} iwn_bands[] = { 2021 /* 20MHz channels, 2GHz band. */ 2022 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 2023 /* 20MHz channels, 5GHz band. */ 2024 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 2025 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 2026 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 2027 { 6, { 145, 149, 153, 157, 161, 165 } }, 2028 /* 40MHz channels (primary channels), 2GHz band. */ 2029 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 2030 /* 40MHz channels (primary channels), 5GHz band. */ 2031 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 2032}; 2033 2034static const uint8_t iwn_bss_ac_to_queue[] = { 2035 2, 3, 1, 0, 2036}; 2037 2038static const uint8_t iwn_pan_ac_to_queue[] = { 2039 5, 4, 6, 7, 2040}; 2041#define IWN1000_OTP_NBLOCKS 3 2042#define IWN6000_OTP_NBLOCKS 4 2043#define IWN6050_OTP_NBLOCKS 7 2044 2045/* HW rate indices. */ 2046#define IWN_RIDX_CCK1 0 2047#define IWN_RIDX_OFDM6 4 2048 2049#define IWN4965_MAX_PWR_INDEX 107 2050#define IWN_POWERSAVE_LVL_NONE 0 2051#define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 2052#define IWN_POWERSAVE_LVL_MAX 5 2053 2054#define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 2055 2056/* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 2057#define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 2058 2059/* 2060 * RF Tx gain values from highest to lowest power (values obtained from 2061 * the reference driver.) 2062 */ 2063static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2064 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 2065 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 2066 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 2067 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 2068 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 2069 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 2070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2073 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2074}; 2075 2076static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2077 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 2078 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 2079 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 2080 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 2081 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 2082 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 2083 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 2084 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 2085 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 2086 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2087}; 2088 2089/* 2090 * DSP pre-DAC gain values from highest to lowest power (values obtained 2091 * from the reference driver.) 2092 */ 2093static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2094 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2095 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2096 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2097 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2098 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2099 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2100 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 2101 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 2102 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 2103 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 2104}; 2105 2106static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2107 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2108 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2109 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2110 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2111 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2112 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2113 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2114 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2115 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2116 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 2117}; 2118 2119/* 2120 * Power saving settings (values obtained from the reference driver.) 2121 */ 2122#define IWN_NDTIMRANGES 3 2123#define IWN_NPOWERLEVELS 6 2124static const struct iwn_pmgt { 2125 uint32_t rxtimeout; 2126 uint32_t txtimeout; 2127 uint32_t intval[5]; 2128 int skip_dtim; 2129} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 2130 /* DTIM <= 2 */ 2131 { 2132 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2133 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 2134 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 2135 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 2136 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 2137 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 2138 }, 2139 /* 3 <= DTIM <= 10 */ 2140 { 2141 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2142 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 2143 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 2144 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 2145 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 2146 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 2147 }, 2148 /* DTIM >= 11 */ 2149 { 2150 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2151 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 2152 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 2153 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 2154 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 2155 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 2156 } 2157}; 2158 2159struct iwn_sensitivity_limits { 2160 uint32_t min_ofdm_x1; 2161 uint32_t max_ofdm_x1; 2162 uint32_t min_ofdm_mrc_x1; 2163 uint32_t max_ofdm_mrc_x1; 2164 uint32_t min_ofdm_x4; 2165 uint32_t max_ofdm_x4; 2166 uint32_t min_ofdm_mrc_x4; 2167 uint32_t max_ofdm_mrc_x4; 2168 uint32_t min_cck_x4; 2169 uint32_t max_cck_x4; 2170 uint32_t min_cck_mrc_x4; 2171 uint32_t max_cck_mrc_x4; 2172 uint32_t min_energy_cck; 2173 uint32_t energy_cck; 2174 uint32_t energy_ofdm; 2175 uint32_t barker_mrc; 2176}; 2177 2178/* 2179 * RX sensitivity limits (values obtained from the reference driver.) 2180 */ 2181static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 2182 105, 140, 2183 220, 270, 2184 85, 120, 2185 170, 210, 2186 125, 200, 2187 200, 400, 2188 97, 2189 100, 2190 100, 2191 390 2192}; 2193 2194static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 2195 120, 120, /* min = max for performance bug in DSP. */ 2196 240, 240, /* min = max for performance bug in DSP. */ 2197 90, 120, 2198 170, 210, 2199 125, 200, 2200 170, 400, 2201 95, 2202 95, 2203 95, 2204 390 2205}; 2206 2207static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 2208 105, 105, /* min = max for performance bug in DSP. */ 2209 220, 220, /* min = max for performance bug in DSP. */ 2210 90, 120, 2211 170, 210, 2212 125, 200, 2213 170, 400, 2214 95, 2215 95, 2216 95, 2217 390, 2218}; 2219 2220static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 2221 120, 155, 2222 240, 290, 2223 90, 120, 2224 170, 210, 2225 125, 200, 2226 170, 400, 2227 95, 2228 95, 2229 95, 2230 390, 2231}; 2232 2233static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 2234 105, 110, 2235 192, 232, 2236 80, 145, 2237 128, 232, 2238 125, 175, 2239 160, 310, 2240 97, 2241 97, 2242 100, 2243 390 2244}; 2245 2246static const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = { 2247 105, 110, 2248 192, 232, 2249 80, 145, 2250 128, 232, 2251 125, 175, 2252 160, 310, 2253 100, 2254 110, 2255 110, 2256 336 2257}; 2258 2259 2260/* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 2261static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 2262 105,110, 2263 128,232, 2264 80,145, 2265 128,232, 2266 125,175, 2267 160,310, 2268 97, 2269 97, 2270 110, 2271 390 2272}; 2273 2274/* Map TID to TX scheduler's FIFO. */ 2275static const uint8_t iwn_tid2fifo[] = { 2276 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 2277}; 2278 2279/* WiFi/WiMAX coexist event priority table for 6050. */ 2280static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2281 { 0x04, 0x03, 0x00, 0x00 }, 2282 { 0x04, 0x03, 0x00, 0x03 }, 2283 { 0x04, 0x03, 0x00, 0x03 }, 2284 { 0x04, 0x03, 0x00, 0x03 }, 2285 { 0x04, 0x03, 0x00, 0x00 }, 2286 { 0x04, 0x03, 0x00, 0x07 }, 2287 { 0x04, 0x03, 0x00, 0x00 }, 2288 { 0x04, 0x03, 0x00, 0x03 }, 2289 { 0x04, 0x03, 0x00, 0x03 }, 2290 { 0x04, 0x03, 0x00, 0x00 }, 2291 { 0x06, 0x03, 0x00, 0x07 }, 2292 { 0x04, 0x03, 0x00, 0x00 }, 2293 { 0x06, 0x06, 0x00, 0x03 }, 2294 { 0x04, 0x03, 0x00, 0x07 }, 2295 { 0x04, 0x03, 0x00, 0x00 }, 2296 { 0x04, 0x03, 0x00, 0x00 } 2297}; 2298 2299/* Firmware errors. */ 2300static const char * const iwn_fw_errmsg[] = { 2301 "OK", 2302 "FAIL", 2303 "BAD_PARAM", 2304 "BAD_CHECKSUM", 2305 "NMI_INTERRUPT_WDG", 2306 "SYSASSERT", 2307 "FATAL_ERROR", 2308 "BAD_COMMAND", 2309 "HW_ERROR_TUNE_LOCK", 2310 "HW_ERROR_TEMPERATURE", 2311 "ILLEGAL_CHAN_FREQ", 2312 "VCC_NOT_STABLE", 2313 "FH_ERROR", 2314 "NMI_INTERRUPT_HOST", 2315 "NMI_INTERRUPT_ACTION_PT", 2316 "NMI_INTERRUPT_UNKNOWN", 2317 "UCODE_VERSION_MISMATCH", 2318 "HW_ERROR_ABS_LOCK", 2319 "HW_ERROR_CAL_LOCK_FAIL", 2320 "NMI_INTERRUPT_INST_ACTION_PT", 2321 "NMI_INTERRUPT_DATA_ACTION_PT", 2322 "NMI_TRM_HW_ER", 2323 "NMI_INTERRUPT_TRM", 2324 "NMI_INTERRUPT_BREAKPOINT", 2325 "DEBUG_0", 2326 "DEBUG_1", 2327 "DEBUG_2", 2328 "DEBUG_3", 2329 "ADVANCED_SYSASSERT" 2330}; 2331 2332/* Find least significant bit that is set. */ 2333#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2334 2335#define IWN_READ(sc, reg) \ 2336 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2337 2338#define IWN_WRITE(sc, reg, val) \ 2339 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2340 2341#define IWN_WRITE_1(sc, reg, val) \ 2342 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2343 2344#define IWN_SETBITS(sc, reg, mask) \ 2345 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2346 2347#define IWN_CLRBITS(sc, reg, mask) \ 2348 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2349 2350#define IWN_BARRIER_WRITE(sc) \ 2351 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2352 BUS_SPACE_BARRIER_WRITE) 2353 2354#define IWN_BARRIER_READ_WRITE(sc) \ 2355 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2356 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2357 2358#endif /* __IF_IWNREG_H__ */ 2359