Searched refs:clk (Results 226 - 250 of 4090) sorted by relevance

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/linux-master/drivers/gpu/drm/logicvc/
H A Dlogicvc_drm.h57 struct clk *vclk;
58 struct clk *vclk2;
59 struct clk *lvdsclk;
60 struct clk *lvdsclkn;
/linux-master/drivers/clk/bcm/
H A Dclk-bcm63xx.c4 #include <linux/clk-provider.h>
6 #include "clk-iproc.h"
/linux-master/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.h15 struct clk;
62 struct clk *apb_clk;
63 struct clk *vid_clk;
65 struct clk *aud_clk;
/linux-master/drivers/clk/axs10x/
H A Di2s_pll_clock.c10 #include <linux/clk-provider.h>
64 static inline void i2s_pll_write(struct i2s_pll_clk *clk, unsigned int reg, argument
67 writel_relaxed(val, clk->base + reg);
70 static inline unsigned int i2s_pll_read(struct i2s_pll_clk *clk, argument
73 return readl_relaxed(clk->base + reg);
101 struct i2s_pll_clk *clk = to_i2s_pll_clk(hw); local
104 idiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_IDIV_REG));
105 fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG));
106 odiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_ODIV0_REG));
114 struct i2s_pll_clk *clk local
133 struct i2s_pll_clk *clk = to_i2s_pll_clk(hw); local
169 struct clk *clk; local
[all...]
/linux-master/drivers/clk/meson/
H A Dmeson-clkc-utils.h10 #include <linux/clk-provider.h>
H A Dmeson-eeclk.h10 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
/linux-master/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_crtc.h23 struct clk;
59 struct clk *aclk;
60 struct clk *pclk;
61 struct clk *dclk;
/linux-master/drivers/pwm/
H A Dpwm-clk.c17 * - The clk API doesn't expose the necessary calls to implement
27 #include <linux/clk.h>
31 struct clk *clk; member in struct:pwm_clk_chip
51 clk_disable(pcchip->clk);
56 ret = clk_enable(pcchip->clk);
63 * We have to enable the clk before setting the rate and duty_cycle,
64 * that however results in a window where the clk is on with a
70 ret = clk_set_rate(pcchip->clk, rate);
77 return clk_set_duty_cycle(pcchip->clk, duty_cycl
[all...]
/linux-master/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c3 // mt8192-afe-clk.c -- Mediatek 8192 afe clock ctrl
10 #include <linux/clk.h>
14 #include "mt8192-afe-clk.h"
69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
70 afe_priv->clk[clk_id]);
86 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
93 afe_priv->clk[CLK_TOP_APLL1_CK]);
102 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG
[all...]
/linux-master/drivers/clk/qcom/
H A Dclk-regmap-mux-div.h10 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
37 struct clk *pclk;
/linux-master/arch/sh/boards/
H A Dboard-apsh4ad0a.c16 #include <linux/clk.h>
100 struct clk *clk; local
103 clk = clk_get(NULL, "extal");
104 if (IS_ERR(clk))
105 return PTR_ERR(clk);
106 ret = clk_set_rate(clk, 33333000);
107 clk_put(clk);
/linux-master/drivers/clk/versatile/
H A Dclk-icst.h30 struct clk *icst_clk_register(struct device *dev,
36 struct clk *icst_clk_setup(struct device *dev,
/linux-master/drivers/media/platform/mediatek/mdp/
H A Dmtk_mdp_comp.h28 * @clk: clocks required for component
34 struct clk *clk[2]; member in struct:mtk_mdp_comp
/linux-master/sound/soc/mediatek/mt8195/
H A DMakefile5 mt8195-audsys-clk.o \
6 mt8195-afe-clk.o \
/linux-master/sound/soc/mediatek/mt8188/
H A DMakefile5 mt8188-afe-clk.o \
7 mt8188-audsys-clk.o \
/linux-master/drivers/remoteproc/
H A Dst_slim_rproc.c10 #include <linux/clk.h>
59 int clk, err; local
61 for (clk = 0; clk < ST_SLIM_MAX_CLK; clk++) {
62 slim_rproc->clks[clk] = of_clk_get(dev->of_node, clk);
63 if (IS_ERR(slim_rproc->clks[clk])) {
64 err = PTR_ERR(slim_rproc->clks[clk]);
67 slim_rproc->clks[clk]
83 int clk; local
91 int clk, ret; local
317 int clk; local
[all...]
/linux-master/drivers/sh/
H A DMakefile7 obj-$(CONFIG_HAVE_CLK) += clk/
/linux-master/drivers/ufs/host/
H A Dti-j721e-ufs.c6 #include <linux/clk.h>
23 struct clk *clk; local
37 clk = devm_clk_get(dev, NULL);
38 if (IS_ERR(clk)) {
39 ret = PTR_ERR(clk);
43 clk_rate = clk_get_rate(clk);
46 devm_clk_put(dev, clk);
/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
165 static struct clk *clk[LPC32XX_CLK_MAX]; variable in typeref:struct:clk
167 .clks = clk,
171 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
378 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk) argument
383 static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val) argument
390 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); local
393 regmap_read(clk_regmap, clk
404 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); local
412 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); local
428 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); local
447 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); local
454 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); local
475 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); local
535 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); local
585 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); local
648 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); local
715 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); local
727 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); local
748 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); local
770 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); local
799 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); local
838 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); local
851 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); local
886 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); local
895 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); local
904 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); local
1059 struct lpc32xx_clk clk; member in union:clk_hw_proto0::__anon302
1387 struct clk *clk; local
[all...]
/linux-master/drivers/clk/sunxi/
H A Dclk-a10-mod1.c8 #include <linux/clk-provider.h>
23 struct clk *clk; local
54 clk = clk_register_composite(NULL, clk_name, parents, i,
58 if (IS_ERR(clk))
61 of_clk_add_provider(node, of_clk_src_simple_get, clk);
72 CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk",
H A Dclk-a10-hosc.c8 #include <linux/clk-provider.h>
19 struct clk *clk; local
44 clk = clk_register_composite(NULL, clk_name,
50 if (IS_ERR(clk))
53 of_clk_add_provider(node, of_clk_src_simple_get, clk);
62 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
H A Dclk-sun6i-ar100.c11 #include <linux/clk-provider.h>
17 #include "clk-factors.h"
75 struct clk *clk; local
81 clk = sunxi_factors_register(np, &sun6i_ar100_data, &sun6i_ar100_lock,
83 if (!clk)
86 platform_set_drvdata(pdev, clk);
92 { .compatible = "allwinner,sun6i-a31-ar100-clk" },
98 .name = "sun6i-a31-ar100-clk",
/linux-master/drivers/clk/microchip/
H A Dclk-core.h9 #include <linux/clk-provider.h>
65 struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *data,
67 struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data,
69 struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data,
71 struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data,
73 struct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data,
/linux-master/drivers/gpu/drm/tegra/
H A Dhub.h43 struct clk *clk_disp;
44 struct clk *clk_dsc;
45 struct clk *clk_hub;
49 struct clk **clk_heads;
66 struct clk *clk; member in struct:tegra_display_hub_state
/linux-master/drivers/clk/ux500/
H A Dclk.h15 struct clk;
18 struct clk *clk_reg_prcc_pclk(const char *name,
24 struct clk *clk_reg_prcc_kclk(const char *name,
68 struct clk *clk_reg_sysctrl_gate(struct device *dev,
77 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
87 struct clk *clk_reg_sysctrl_set_parent(struct device *dev,

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