/u-boot/arch/arm/mach-apple/ |
H A D | sart.c | 43 uintptr_t base; member in struct:apple_sart 55 u32 cfg = readl(sart->base + APPLE_SART2_CONFIG(index)); 59 ((u64)readl(sart->base + APPLE_SART2_PADDR(index)) << APPLE_SART2_PADDR_SHIFT); 82 writel(paddr, sart->base + APPLE_SART2_PADDR(index)); 83 writel(cfg, sart->base + APPLE_SART2_CONFIG(index)); 91 *flags = readl(sart->base + APPLE_SART3_CONFIG(index)); 92 *size = (size_t)readl(sart->base + APPLE_SART3_SIZE(index)) << APPLE_SART3_SIZE_SHIFT; 94 ((u64)readl(sart->base + APPLE_SART3_PADDR(index)) << APPLE_SART3_PADDR_SHIFT); 113 writel(paddr, sart->base + APPLE_SART3_PADDR(index)); 114 writel(size, sart->base 122 phys_addr_t base; local [all...] |
/u-boot/arch/arm/mach-nexell/include/mach/ |
H A D | display_dev.h | 12 unsigned long base; member in struct:nx_display_dev
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/u-boot/drivers/clk/at91/ |
H A D | pmc.h | 110 sam9x60_clk_register_usb(void __iomem *base, const char *name, 115 sam9x60_clk_register_div_pll(void __iomem *base, const char *name, 120 sam9x60_clk_register_frac_pll(void __iomem *base, const char *name, 125 at91_clk_register_master_pres(void __iomem *base, const char *name, 131 at91_clk_register_master_div(void __iomem *base, 136 at91_clk_sama7g5_register_master(void __iomem *base, const char *name, 141 at91_clk_register_utmi(void __iomem *base, struct udevice *dev, 144 at91_clk_sama7g5_register_utmi(void __iomem *base, const char *name, 147 at91_clk_register_programmable(void __iomem *base, const char *name, 152 at91_clk_register_system(void __iomem *base, cons [all...] |
H A D | pmc.c | 34 * pmc_read() - read content at address base + off into val 36 * @base: base address 38 * @val: where the content of base + off is stored 42 void pmc_read(void __iomem *base, unsigned int off, unsigned int *val) argument 44 *val = readl(base + off); 48 * pmc_write() - write content of val at address base + off 50 * @base: base address 52 * @val: content to be written at base 56 pmc_write(void __iomem *base, unsigned int off, unsigned int val) argument 71 pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask, unsigned int bits) argument [all...] |
/u-boot/include/configs/ |
H A D | rpi.h | 13 #include <asm/arch/base.h>
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/u-boot/drivers/rng/ |
H A D | jh7110_rng.c | 81 void *base; member in struct:starfive_trng_plat 92 return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat, 100 u32 data = readl(trng->base + STARFIVE_ISTAT); 102 writel(data, trng->base + STARFIVE_ISTAT); 112 writel(cmd, trng->base + STARFIVE_CTRL); 116 writel(cmd, trng->base + STARFIVE_CTRL); 123 ret = readl_relaxed_poll_timeout(trng->base + STARFIVE_ISTAT, stat, 125 writel(flg, trng->base + STARFIVE_ISTAT); 153 val = readl(trng->base + STARFIVE_RAND0 + 169 writel(0, trng->base [all...] |
/u-boot/arch/arm/mach-bcm283x/include/mach/ |
H A D | wdog.h | 9 #include <asm/arch/base.h>
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/u-boot/include/ |
H A D | dwc3-omap-uboot.h | 22 void *base; member in struct:dwc3_omap_device
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H A D | ram.h | 13 phys_addr_t base; member in struct:ram_info
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/u-boot/drivers/timer/ |
H A D | arm_twd_timer.c | 51 struct arm_twd_timer_regs *base; member in struct:arm_twd_timer_priv 57 struct arm_twd_timer_regs *regs = priv->base; 73 priv->base = (struct arm_twd_timer_regs *)addr; 75 regs = priv->base;
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H A D | mtk_timer.c | 34 void __iomem *base; member in struct:mtk_timer_priv 41 u32 val = readl(priv->base + priv->gpt4_offset + MTK_GPT_CNT); 53 priv->base = dev_read_addr_ptr(dev); 56 if (!priv->base) 63 priv->base + priv->gpt4_offset + MTK_GPT_CON); 68 priv->base + priv->gpt4_offset + MTK_GPT_CON); 69 writel(0, priv->base + priv->gpt4_offset + MTK_GPT_V1_CLK);
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/u-boot/board/samsung/goni/ |
H A D | onenand.c | 17 this->base = (void *)CFG_SYS_ONENAND_BASE;
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/u-boot/board/samsung/universal_c210/ |
H A D | onenand.c | 16 this->base = (void *)CFG_SYS_ONENAND_BASE;
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/u-boot/arch/x86/cpu/intel_common/ |
H A D | fast_spi.c | 37 ulong base; local 39 base = fast_spi_get_bios_region(regs, map_sizep); 40 *map_basep = (u32)-*map_sizep - base; 41 *offsetp = base;
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/u-boot/drivers/bootcount/ |
H A D | bootcount.c | 60 * @base: base address used for bootcounter 64 phys_addr_t base; member in struct:bootcount_mem_priv 71 void *reg = (void *)priv->base; 94 void *reg = (void *)priv->base; 96 uintptr_t flush_start = rounddown(priv->base, 102 flush_end = roundup(priv->base + 4, 107 flush_end = roundup(priv->base + 8, 124 priv->base = (phys_addr_t)dev_read_addr(dev);
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/u-boot/drivers/reset/ |
H A D | reset-npcm.c | 12 void __iomem *base; member in struct:npcm_reset_priv 31 val = readl(priv->base + rst->id); 33 writel(val, priv->base + rst->id); 44 val = readl(priv->base + rst->id); 46 writel(val, priv->base + rst->id); 70 priv->base = dev_remap_addr(dev); 71 if (!priv->base)
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/u-boot/drivers/clk/renesas/ |
H A D | renesas-cpg-mssr.c | 93 int renesas_clk_endisable(struct clk *clk, void __iomem *base, argument 108 clrbits_le32(base + info->control_regs[reg], bitmask); 109 return wait_for_bit_le32(base + info->status_regs[reg], 112 setbits_le32(base + info->control_regs[reg], bitmask); 117 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info) argument 126 clrsetbits_le32(base + info->control_regs[i], 133 clrsetbits_le32(base + RMSTPCR(i),
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/u-boot/drivers/clk/qcom/ |
H A D | clock-qcom.h | 84 phys_addr_t base; member in struct:msm_clk_priv 89 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); 92 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); 94 void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, 96 void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, 105 val = readl(priv->base + priv->data->clks[id].reg); 106 writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
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/u-boot/drivers/pci/ |
H A D | pcie_plda_common.c | 85 void __iomem *base = local 94 base += XR3PCI_ATR_TABLE_OFFSET * plda->atr_table_num; 106 base + XR3PCI_ATR_SRC_ADDR_LOW); 107 writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH); 109 base + XR3PCI_ATR_TRSL_ADDR_LOW); 110 writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH); 111 writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
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/u-boot/drivers/mtd/nand/raw/brcmnand/ |
H A D | bcm6368_nand.c | 18 void __iomem *base; member in struct:bcm6368_nand_soc 43 void __iomem *mmio = priv->base + BCM6368_NAND_INT; 60 void __iomem *mmio = priv->base + BCM6368_NAND_INT; 79 priv->base = dev_remap_addr_name(dev, "nand-int-base"); 80 if (!priv->base) 87 brcmnand_writel(0, priv->base + BCM6368_NAND_INT); 89 priv->base + BCM6368_NAND_INT);
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/u-boot/drivers/clk/microchip/ |
H A D | mpfs_clk_msspll.c | 44 void __iomem *base; member in struct:mpfs_msspll_hw_clock 60 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 61 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 62 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 91 int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent) argument 98 mpfs_msspll_clks[0].base = base;
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/u-boot/drivers/clk/mtmips/ |
H A D | clk-mt7628.c | 34 void __iomem *base; member in struct:mt7628_clk_priv 71 val = readl(priv->base + CLKCFG0_REG); 88 setbits_32(priv->base + CLKCFG1_REG, BIT(clk->id)); 100 clrbits_32(priv->base + CLKCFG1_REG, BIT(clk->id)); 117 priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); 118 if (!priv->base) 131 val = readl(priv->base + CLKCFG0_REG);
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/u-boot/arch/x86/lib/ |
H A D | sfi.c | 25 u32 base; member in struct:table_info 36 tab->entry_start = tab->base + tab->ptr; 47 hdr = (struct sfi_table_header *)(uintptr_t)(tab->base + tab->ptr); 133 ulong write_sfi_table(ulong base) argument 137 table.base = base; 152 return base + table.ptr;
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/u-boot/arch/mips/mach-mtmips/mt7620/ |
H A D | sysc.c | 19 void __iomem *base; member in struct:mt7620_sysc_priv 32 val = readl(priv->base + offset); 51 writel(val, priv->base + offset); 73 val = readl(priv->base + SYSCTL_CLKCFG0_REG); 84 val = readl(priv->base + SYSCTL_CHIP_REV_ID_REG); 104 clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, 117 clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, 130 clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, 144 priv->base = dev_remap_addr_index(dev, 0); 145 if (!priv->base) { [all...] |
/u-boot/drivers/phy/qcom/ |
H A D | phy-qcom-usb-ss.c | 30 void __iomem *base; member in struct:ssphy_priv 75 writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); 76 ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); 77 ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); 78 ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); 87 ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); 88 ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); 89 ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); 118 priv->base = dev_read_addr_ptr(dev); 119 if (!priv->base) [all...] |