1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2022 Sumit Garg <sumit.garg@linaro.org> 4 * 5 * Based on Linux driver 6 */ 7 8#include <common.h> 9#include <dm.h> 10#include <generic-phy.h> 11#include <linux/bitops.h> 12#include <asm/io.h> 13#include <reset.h> 14#include <clk.h> 15#include <linux/delay.h> 16 17#define PHY_CTRL0 0x6C 18#define PHY_CTRL1 0x70 19#define PHY_CTRL2 0x74 20#define PHY_CTRL4 0x7C 21 22/* PHY_CTRL bits */ 23#define REF_PHY_EN BIT(0) 24#define LANE0_PWR_ON BIT(2) 25#define SWI_PCS_CLK_SEL BIT(4) 26#define TST_PWR_DOWN BIT(4) 27#define PHY_RESET BIT(7) 28 29struct ssphy_priv { 30 void __iomem *base; 31 struct clk_bulk clks; 32 struct reset_ctl com_rst; 33 struct reset_ctl phy_rst; 34}; 35 36static inline void ssphy_updatel(void __iomem *addr, u32 mask, u32 val) 37{ 38 writel((readl(addr) & ~mask) | val, addr); 39} 40 41static int ssphy_do_reset(struct ssphy_priv *priv) 42{ 43 int ret; 44 45 ret = reset_assert(&priv->com_rst); 46 if (ret) 47 return ret; 48 49 ret = reset_assert(&priv->phy_rst); 50 if (ret) 51 return ret; 52 53 udelay(10); 54 55 ret = reset_deassert(&priv->com_rst); 56 if (ret) 57 return ret; 58 59 ret = reset_deassert(&priv->phy_rst); 60 if (ret) 61 return ret; 62 63 return 0; 64} 65 66static int ssphy_power_on(struct phy *phy) 67{ 68 struct ssphy_priv *priv = dev_get_priv(phy->dev); 69 int ret; 70 71 ret = ssphy_do_reset(priv); 72 if (ret) 73 return ret; 74 75 writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); 76 ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); 77 ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); 78 ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); 79 80 return 0; 81} 82 83static int ssphy_power_off(struct phy *phy) 84{ 85 struct ssphy_priv *priv = dev_get_priv(phy->dev); 86 87 ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); 88 ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); 89 ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); 90 91 return 0; 92} 93 94static int ssphy_clk_init(struct udevice *dev, struct ssphy_priv *priv) 95{ 96 int ret; 97 98 ret = clk_get_bulk(dev, &priv->clks); 99 if (ret == -ENOSYS || ret == -ENOENT) 100 return 0; 101 if (ret) 102 return ret; 103 104 ret = clk_enable_bulk(&priv->clks); 105 if (ret) { 106 clk_release_bulk(&priv->clks); 107 return ret; 108 } 109 110 return 0; 111} 112 113static int ssphy_probe(struct udevice *dev) 114{ 115 struct ssphy_priv *priv = dev_get_priv(dev); 116 int ret; 117 118 priv->base = dev_read_addr_ptr(dev); 119 if (!priv->base) 120 return -EINVAL; 121 122 ret = ssphy_clk_init(dev, priv); 123 if (ret) 124 return ret; 125 126 ret = reset_get_by_name(dev, "com", &priv->com_rst); 127 if (ret) 128 return ret; 129 130 ret = reset_get_by_name(dev, "phy", &priv->phy_rst); 131 if (ret) 132 return ret; 133 134 return 0; 135} 136 137static struct phy_ops ssphy_ops = { 138 .power_on = ssphy_power_on, 139 .power_off = ssphy_power_off, 140}; 141 142static const struct udevice_id ssphy_ids[] = { 143 { .compatible = "qcom,usb-ss-28nm-phy" }, 144 { } 145}; 146 147U_BOOT_DRIVER(qcom_usb_ss) = { 148 .name = "qcom-usb-ss", 149 .id = UCLASS_PHY, 150 .of_match = ssphy_ids, 151 .ops = &ssphy_ops, 152 .probe = ssphy_probe, 153 .priv_auto = sizeof(struct ssphy_priv), 154}; 155