Searched refs:barrier (Results 226 - 250 of 545) sorted by path
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| /linux-master/arch/sh/include/asm/ |
| H A D | processor.h | 95 #define cpu_relax() barrier()
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| /linux-master/arch/sh/kernel/ |
| H A D | smp.c | 236 barrier();
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| /linux-master/arch/sparc/include/asm/ |
| H A D | atomic_32.h | 18 #include <asm/barrier.h>
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| H A D | atomic_64.h | 13 #include <asm/barrier.h>
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| H A D | bitops_64.h | 17 #include <asm/barrier.h>
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| H A D | processor_32.h | 94 #define cpu_relax() barrier()
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| H A D | spinlock_64.h | 13 #include <asm/barrier.h>
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| H A D | vvar.h | 10 #include <asm/barrier.h>
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| /linux-master/arch/sparc/kernel/ |
| H A D | ds.c | 824 barrier();
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| H A D | leon_smp.c | 427 barrier();
436 barrier();
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| H A D | perf_event.c | 1038 barrier();
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| H A D | process_64.c | 234 barrier();
335 barrier();
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| H A D | smp_64.c | 1337 barrier();
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| H A D | sun4d_smp.c | 83 barrier();
86 barrier();
104 barrier();
337 barrier();
345 barrier();
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| H A D | sun4m_smp.c | 216 barrier();
224 barrier();
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| /linux-master/arch/um/include/shared/ |
| H A D | user.h | 58 #define barrier() __asm__ __volatile__("": : :"memory") macro
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| /linux-master/arch/um/os-Linux/ |
| H A D | sigio.c | 523 !({ barrier(); got_sigio; }))
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| H A D | signal.c | 272 * This must return with signals disabled, so this barrier
277 barrier();
303 * happen in this order, so have the barrier here.
305 barrier();
391 barrier();
400 barrier();
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| /linux-master/arch/x86/events/ |
| H A D | core.c | 729 barrier();
1354 barrier();
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| /linux-master/arch/x86/events/intel/ |
| H A D | bts.c | 214 * Since BTS is coherent, just add compiler barrier to ensure
217 barrier();
229 * - is ordered against bts::handle::event with a compiler barrier.
248 * local barrier to make sure that ds configuration made it
506 barrier();
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| /linux-master/arch/x86/include/asm/ |
| H A D | atomic.h | 10 #include <asm/barrier.h>
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| H A D | barrier.h | 51 /* Prevent speculative execution past this barrier. */
54 #define __dma_rmb() barrier()
55 #define __dma_wmb() barrier()
60 #define __smp_wmb() barrier()
66 barrier(); \
74 barrier(); \
82 /* Writing to CR3 provides a full memory barrier in switch_mm(). */
85 #include <asm-generic/barrier.h>
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| H A D | bitops.h | 19 #include <asm/barrier.h>
87 barrier();
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| H A D | debugreg.h | 136 barrier();
148 barrier();
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| H A D | io.h | 46 #define build_mmio_read(name, size, type, reg, barrier) \
49 :"m" (*(volatile type __force *)addr) barrier); return ret; }
51 #define build_mmio_write(name, size, type, reg, barrier) \
54 "m" (*(volatile type __force *)addr) barrier); }
369 * time. Order of access is not guaranteed, nor is a memory barrier
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