/linux-master/drivers/regulator/ |
H A D | rt5739.c | 55 unsigned int mask, val; local 58 mask = RT5739_MODEVSEL0_MASK; 60 mask = RT5739_MODEVSEL1_MASK; 64 val = mask; 73 return regmap_update_bits(regmap, RT5739_REG_CNTL1, mask, val); 80 unsigned int mask, val; local 84 mask = RT5739_MODEVSEL0_MASK; 86 mask = RT5739_MODEVSEL1_MASK; 92 if (val & mask) 123 unsigned int mask; local 137 unsigned int mask; local 152 unsigned int mask, val; local [all...] |
H A D | rohm-regulator.c | 13 char *prop, unsigned int reg, unsigned int mask, 31 if (!mask) { 49 ret = regmap_update_bits(regmap, reg, mask, i); 66 unsigned int reg, mask, omask, oreg = desc->enable_reg; local 77 mask = dvs->run_mask; 83 mask = dvs->idle_mask; 89 mask = dvs->suspend_mask; 95 mask = dvs->lpsr_mask; 101 mask = dvs->snvs_mask; 107 ret = set_dvs_level(desc, np, regmap, prop, reg, mask, 11 set_dvs_level(const struct regulator_desc *desc, struct device_node *np, struct regmap *regmap, char *prop, unsigned int reg, unsigned int mask, unsigned int omask, unsigned int oreg) argument [all...] |
/linux-master/drivers/mfd/ |
H A D | max8907.c | 115 { .reg_offset = 0, .mask = 1 << 0, }, 116 { .reg_offset = 0, .mask = 1 << 1, }, 117 { .reg_offset = 0, .mask = 1 << 2, }, 118 { .reg_offset = 1, .mask = 1 << 0, }, 119 { .reg_offset = 1, .mask = 1 << 1, }, 120 { .reg_offset = 1, .mask = 1 << 2, }, 121 { .reg_offset = 1, .mask = 1 << 3, }, 122 { .reg_offset = 1, .mask = 1 << 4, }, 123 { .reg_offset = 1, .mask = 1 << 5, }, 124 { .reg_offset = 1, .mask [all...] |
H A D | max77693.c | 58 { .mask = LED_IRQ_FLED2_OPEN, }, 59 { .mask = LED_IRQ_FLED2_SHORT, }, 60 { .mask = LED_IRQ_FLED1_OPEN, }, 61 { .mask = LED_IRQ_FLED1_SHORT, }, 62 { .mask = LED_IRQ_MAX_FLASH, }, 75 { .mask = TOPSYS_IRQ_T120C_INT, }, 76 { .mask = TOPSYS_IRQ_T140C_INT, }, 77 { .mask = TOPSYS_IRQ_LOWSYS_INT, }, 90 { .mask = CHG_IRQ_BYP_I, }, 91 { .mask [all...] |
H A D | max8998-irq.c | 16 int mask; member in struct:max8998_irq_data 22 .mask = MAX8998_IRQ_DCINF_MASK, 26 .mask = MAX8998_IRQ_DCINR_MASK, 30 .mask = MAX8998_IRQ_JIGF_MASK, 34 .mask = MAX8998_IRQ_JIGR_MASK, 38 .mask = MAX8998_IRQ_PWRONF_MASK, 42 .mask = MAX8998_IRQ_PWRONR_MASK, 46 .mask = MAX8998_IRQ_WTSREVNT_MASK, 50 .mask = MAX8998_IRQ_SMPLEVNT_MASK, 54 .mask [all...] |
/linux-master/arch/mips/sgi-ip27/ |
H A D | ip27-irq.c | 55 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); local 57 set_bit(d->hwirq, mask); 58 __raw_writeq(mask[0], hd->irq_mask[0]); 59 __raw_writeq(mask[1], hd->irq_mask[1]); 65 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); local 67 clear_bit(d->hwirq, mask); 68 __raw_writeq(mask[0], hd->irq_mask[0]); 69 __raw_writeq(mask[1], hd->irq_mask[1]); 72 static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask) argument 77 cpu = cpumask_first_and(mask, cpu_online_mas 92 set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask, bool force) argument 192 unsigned long *mask = per_cpu(irq_enable_mask, cpu); local 232 unsigned long *mask = per_cpu(irq_enable_mask, cpu); local 255 unsigned long *mask = per_cpu(irq_enable_mask, cpu); local [all...] |
/linux-master/drivers/iio/imu/st_lsm6dsx/ |
H A D | st_lsm6dsx_core.c | 124 .mask = BIT(0), 128 .mask = BIT(7), 132 .mask = BIT(6), 159 .mask = GENMASK(7, 5), 172 .mask = GENMASK(7, 5), 187 .mask = GENMASK(4, 3), 198 .mask = GENMASK(4, 3), 210 .mask = BIT(3), 214 .mask = BIT(3), 218 .mask 1798 st_lsm6dsx_read_raw(struct iio_dev *iio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask) argument 1832 st_lsm6dsx_write_raw(struct iio_dev *iio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) argument 2066 st_lsm6dsx_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long mask) argument [all...] |
/linux-master/arch/m68k/include/asm/ |
H A D | atariints.h | 117 { unsigned char mask, *reg; local 119 mask = 1 << (irq & 7); 122 return( *reg & mask ); 127 { unsigned char mask, *reg; local 129 mask = 1 << (irq & 7); 133 : : "di" (mask), "m" (*reg) : "memory" ); 138 { unsigned char mask, *reg; local 140 mask = ~(1 << (irq & 7)); 145 : : "di" (mask), "m" (*reg) : "memory" ); 148 : : "di" (mask), " [all...] |
/linux-master/sound/soc/intel/common/ |
H A D | soc-acpi-intel-sdw-mockup-match.c | 108 .mask = BIT(0), 113 .mask = BIT(1), 118 .mask = BIT(3), 127 .mask = BIT(0), 132 .mask = BIT(1), 137 .mask = BIT(2), 142 .mask = BIT(3), 151 .mask = BIT(1), 156 .mask = BIT(2), 161 .mask [all...] |
H A D | soc-acpi-intel-tgl-match.c | 249 .mask = BIT(0), 254 .mask = BIT(1), 263 .mask = BIT(0), 272 .mask = BIT(0), 277 .mask = BIT(1), 286 .mask = BIT(0), 291 .mask = BIT(1), 300 .mask = BIT(0), 305 .mask = BIT(1), 310 .mask [all...] |
/linux-master/fs/ntfs3/ |
H A D | bitfunc.c | 83 u8 mask; local 89 mask = fill_mask[pos + nbits] & zero_mask[pos]; 90 return !nbits || (*map & mask) == mask; 93 mask = zero_mask[pos]; 94 if ((*map++ & mask) != mask) 122 mask = fill_mask[pos]; 123 if ((*map & mask) != mask) [all...] |
/linux-master/drivers/scsi/lpfc/ |
H A D | lpfc_logmsg.h | 57 #define lpfc_vlog_msg(vport, level, mask, fmt, arg...) \ 58 { if (((mask) & (vport)->cfg_log_verbose) || (level[1] <= '5')) \ 62 #define lpfc_log_msg(phba, level, mask, fmt, arg...) \ 67 if (((mask) & log_verbose) || (level[1] <= '5')) \ 73 #define lpfc_printf_vlog(vport, level, mask, fmt, arg...) \ 75 { if (((mask) & (vport)->cfg_log_verbose) || (level[1] <= '3')) { \ 76 if ((mask) & LOG_TRACE_EVENT && !(vport)->cfg_log_verbose) \ 86 #define lpfc_printf_log(phba, level, mask, fmt, arg...) \ 91 if (((mask) & log_verbose) || (level[1] <= '3')) { \ 92 if ((mask) [all...] |
/linux-master/arch/arm/mach-pxa/ |
H A D | mfp-pxa2xx.c | 45 unsigned int mask; /* bit mask in PWER or PKWR */ member in struct:gpio_desc 46 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */ 56 unsigned long gafr, mask = GPIO_bit(gpio); local 76 GPDR(gpio) |= mask; 78 GPDR(gpio) &= ~mask; 83 PGSR(bank) |= mask; 87 PGSR(bank) &= ~mask; 101 gpdr_lpm[bank] |= mask; 103 gpdr_lpm[bank] &= ~mask; 257 unsigned int i, gpio, mask = 0; local [all...] |
/linux-master/sound/soc/intel/avs/ |
H A D | dsp.c | 20 u32 value, mask, reg; local 26 mask = AVS_ADSPCS_SPA_MASK(core_mask); 27 value = power ? mask : 0; 29 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value); 33 mask = AVS_ADSPCS_CPA_MASK(core_mask); 34 value = power ? mask : 0; 37 reg, (reg & mask) == value, 49 u32 value, mask, reg; local 55 mask = AVS_ADSPCS_CRST_MASK(core_mask); 56 value = reset ? mask 73 u32 value, mask, reg; local 125 u32 mask; local 157 u32 mask; local 198 u32 mask; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
H A D | hw_translate_dcn315.c | 67 uint32_t mask, 75 switch (mask) { 105 switch (mask) { 132 switch (mask) { 198 info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK; 225 info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK; 255 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; 258 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; 261 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; 264 info->mask 65 offset_to_id( uint32_t offset, uint32_t mask, enum gpio_id *id, uint32_t *en) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
H A D | hw_translate_dcn30.c | 72 uint32_t mask, 80 switch (mask) { 110 switch (mask) { 137 switch (mask) { 206 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; 236 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; 269 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; 272 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; 275 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; 278 info->mask 70 offset_to_id( uint32_t offset, uint32_t mask, enum gpio_id *id, uint32_t *en) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
H A D | hw_translate_dcn20.c | 67 uint32_t mask, 75 switch (mask) { 105 switch (mask) { 132 switch (mask) { 201 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; 231 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; 264 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; 267 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; 270 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; 273 info->mask 65 offset_to_id( uint32_t offset, uint32_t mask, enum gpio_id *id, uint32_t *en) argument [all...] |
/linux-master/arch/sparc/kernel/ |
H A D | leon_kernel.c | 42 #define LEON_IMASK(cpu) (&leon3_irqctrl_regs->mask[cpu]) 70 unsigned long mask, oldmask; local 82 * controller have a mask-bit of their own, so this is safe. 85 mask = 1 << eirq; 87 LEON3_BYPASS_STORE_PA(LEON_IMASK(boot_cpu_id), (oldmask | mask)); 93 unsigned long mask; local 99 mask = 0; 101 mask = LEON_HARD_INT(irq); 103 return mask; 109 cpumask_t mask; local 124 unsigned long mask, oldmask, flags; local 147 unsigned long mask, oldmask, flags; local 160 unsigned long mask, oldmask, flags; local 187 unsigned long mask = (unsigned long)data->chip_data; local 214 unsigned long mask; local 250 unsigned long mask = (unsigned long)irq_get_chip_data(virq); local 492 unsigned long mask, flags, *addr; local [all...] |
/linux-master/arch/xtensa/include/asm/ |
H A D | bitops.h | 105 unsigned long mask = 1UL << (bit & 31); \ 111 " "insn" %[tmp], %[tmp], %[mask]\n" \ 116 : [mask] "a" (inv mask), [addr] "a" (p) \ 125 unsigned long mask = 1UL << (bit & 31); \ 131 " "insn" %[tmp], %[value], %[mask]\n" \ 136 : [mask] "a" (inv mask), [addr] "a" (p) \ 139 return value & mask; \ 148 unsigned long mask [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_wait_user_fence.c | 18 static int do_compare(u64 addr, u64 value, u64 mask, u16 op) argument 30 passed = (rvalue & mask) == (value & mask); 33 passed = (rvalue & mask) != (value & mask); 36 passed = (rvalue & mask) > (value & mask); 39 passed = (rvalue & mask) >= (value & mask); 42 passed = (rvalue & mask) < (valu [all...] |
/linux-master/net/bridge/netfilter/ |
H A D | ebt_mark_m.c | 22 return !!(skb->mark & info->mask) ^ info->invert; 23 return ((skb->mark & info->mask) == info->mark) ^ info->invert; 42 compat_ulong_t mark, mask; member in struct:compat_ebt_mark_m_info 52 kern->mask = user->mask; 63 put_user(kern->mask, &user->mask) ||
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/linux-master/arch/arm64/kernel/ |
H A D | sleep.S | 19 * @mask: register containing MPIDR mask 25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) { 27 * u64 mpidr_masked = mpidr & mask; 34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask 39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask 40 and \mpidr, \mpidr, \mask // mask out MPIDR bits 41 and \dst, \mpidr, #0xff // mask=aff0 43 and \mask, \mpid [all...] |
/linux-master/fs/hfsplus/ |
H A D | bitmap.c | 26 u32 mask, start, len, n; local 55 mask = (1U << 31) >> i; 56 for (; i < 32; mask >>= 1, i++) { 57 if (!(n & mask)) 69 mask = 1 << 31; 70 for (i = 0; i < 32; mask >>= 1, i++) { 71 if (!(n & mask)) 106 n |= mask; 109 mask >>= 1; 110 if (!--len || n & mask) 170 u32 mask, len, pnr; local [all...] |
/linux-master/drivers/gpio/ |
H A D | gpio-ath79.c | 56 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) 61 new_val = (old_val & ~mask) | (bits & mask); 72 u32 mask = BIT(irqd_to_hwirq(data)); local 77 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 84 u32 mask = BIT(irqd_to_hwirq(data)); local 88 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 96 u32 mask = BIT(irqd_to_hwirq(data)); local 100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mas 55 ath79_gpio_update_bits( struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) argument 108 u32 mask = BIT(irqd_to_hwirq(data)); local 121 u32 mask = BIT(irqd_to_hwirq(data)); local [all...] |
/linux-master/drivers/net/wireless/intel/iwlwifi/ |
H A D | iwl-io.h | 16 static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask) argument 18 iwl_trans_set_bits_mask(trans, reg, mask, mask); 21 static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask) argument 23 iwl_trans_set_bits_mask(trans, reg, mask, 0); 27 u32 bits, u32 mask, int timeout); 28 int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask, 48 u32 bits, u32 mask, int timeout); 49 void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); 51 u32 bits, u32 mask); 94 iwl_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr, u32 bits, u32 mask, int timeout) argument [all...] |