Searched refs:reg_base (Results 176 - 200 of 407) sorted by relevance

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/linux-master/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptpf.h27 void __iomem *reg_base; /* CPT PF registers start address */ member in struct:otx2_cptpf_dev
/linux-master/drivers/gpio/
H A Dgpio-tangier.h92 * @reg_base: Base address of MMIO registers
103 void __iomem *reg_base; member in struct:tng_gpio
/linux-master/drivers/clk/rockchip/
H A Dclk-rk3036.c439 void __iomem *reg_base; local
442 reg_base = of_iomap(np, 0);
443 if (!reg_base) {
453 reg_base + RK2928_CLKSEL_CON(13));
455 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
458 iounmap(reg_base);
480 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
/linux-master/drivers/pci/controller/
H A Dpcie-xilinx.c96 * @reg_base: IO Mapped Register Base
105 void __iomem *reg_base; member in struct:xilinx_pcie
115 return readl(pcie->reg_base + reg);
120 writel(val, pcie->reg_base + reg);
185 return pcie->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
544 pcie->reg_base = devm_pci_remap_cfg_resource(dev, &regs);
545 if (IS_ERR(pcie->reg_base))
546 return PTR_ERR(pcie->reg_base);
/linux-master/drivers/mailbox/
H A Dstm32-ipcc.c51 void __iomem *reg_base; member in struct:stm32_ipcc
238 ipcc->reg_base = devm_platform_ioremap_resource(pdev, 0);
239 if (IS_ERR(ipcc->reg_base))
240 return PTR_ERR(ipcc->reg_base);
242 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
290 ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
314 ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
/linux-master/drivers/dma/
H A Duniphier-mdmac.c70 void __iomem *reg_base; member in struct:uniphier_mdmac_device
141 writel(BIT(mc->chan_id), mdev->reg_base + UNIPHIER_MDMAC_CMD);
165 mdev->reg_base + UNIPHIER_MDMAC_CMD);
371 mc->reg_ch_base = mdev->reg_base + UNIPHIER_MDMAC_CH_OFFSET +
400 mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
401 if (IS_ERR(mdev->reg_base))
402 return PTR_ERR(mdev->reg_base);
/linux-master/drivers/net/can/sja1000/
H A Dkvaser_pci.c108 return ioread8(priv->reg_base + port);
114 iowrite8(val, priv->reg_base + port);
189 pci_iounmap(board->pci_dev, priv->reg_base);
241 priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES;
254 dev_info(&pdev->dev, "reg_base=%p conf_addr=%p irq=%d\n",
255 priv->reg_base, board->conf_addr, dev->irq);
/linux-master/drivers/fpga/
H A Dsocfpga-a10.c472 void __iomem *reg_base; local
481 reg_base = devm_platform_ioremap_resource(pdev, 0);
482 if (IS_ERR(reg_base))
483 return PTR_ERR(reg_base);
491 priv->regmap = devm_regmap_init_mmio(dev, reg_base,
/linux-master/drivers/net/wireless/ath/ath12k/
H A Dhal.c1656 u32 reg_base; local
1658 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
1661 ath12k_hif_write32(ab, reg_base +
1668 ath12k_hif_write32(ab, reg_base +
1672 reg_base + ath12k_hal_reo1_ring_msi1_data_offset(ab),
1676 ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr);
1682 ath12k_hif_write32(ab, reg_base + ath12k_hal_reo1_ring_base_msb_offset(ab), val);
1686 ath12k_hif_write32(ab, reg_base + ath12k_hal_reo1_ring_id_offset(ab), val);
1696 reg_base + ath12k_hal_reo1_ring_producer_int_setup_offset(ab),
1702 ath12k_hif_write32(ab, reg_base
1732 u32 reg_base; local
2293 u32 reg_base; local
[all...]
/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c551 void __iomem *reg_base, int n)
553 void __iomem *reg = reg_base + LPC18XX_CGU_BASE_CLK(n);
640 static void __init lpc18xx_cgu_register_base_clks(void __iomem *reg_base) argument
646 reg_base, i);
654 void __iomem *reg_base; local
656 reg_base = of_iomap(np, 0);
657 if (!reg_base) {
662 lpc18xx_cgu_register_source_clks(np, reg_base);
663 lpc18xx_cgu_register_base_clks(reg_base);
550 lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk, void __iomem *reg_base, int n) argument
/linux-master/drivers/soc/qcom/
H A Dspm.c83 void __iomem *reg_base; member in struct:spm_driver_data
260 writel_relaxed(val, drv->reg_base +
274 writel_relaxed(val, drv->reg_base +
276 ret = readl_relaxed(drv->reg_base +
287 return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
518 drv->reg_base = devm_platform_ioremap_resource(pdev, 0);
519 if (IS_ERR(drv->reg_base))
520 return PTR_ERR(drv->reg_base);
531 addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
/linux-master/drivers/dma/idxd/
H A Dinit.c430 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
431 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
461 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
465 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
482 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
492 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
498 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
509 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
517 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);
736 idxd->reg_base
[all...]
H A Dirq.c369 idxd->reg_base + IDXD_EVLSTATUS_OFFSET + sizeof(u32));
370 evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
382 iowrite32(evl_status.bits_lower32, idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
397 cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
401 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
409 idxd->sw_err.bits[i] = ioread64(idxd->reg_base +
413 idxd->reg_base + IDXD_SWERR_OFFSET);
487 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
/linux-master/arch/sh/drivers/pci/
H A Dpci-sh4.h173 __raw_writel(val, chan->reg_base + reg);
179 return __raw_readl(chan->reg_base + reg);
/linux-master/kernel/irq/
H A Ddevres.c211 * @reg_base: Register base address (virtual)
219 unsigned int irq_base, void __iomem *reg_base,
227 irq_base, reg_base, handler);
218 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler) argument
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c157 this->mmio = ioremap(this->reg_base, this->reg_size);
187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset;
H A Dlsdc_i2c.c114 * @reg_base: gpio reg base
143 li2c->dir_reg = ldev->reg_base + LS7A_DC_GPIO_DIR_REG;
144 li2c->dat_reg = ldev->reg_base + LS7A_DC_GPIO_DAT_REG;
/linux-master/drivers/remoteproc/
H A Dmtk_scp_ipi.c180 ret = readl_poll_timeout_atomic(scp->cluster->reg_base + scp->data->host_to_scp_reg,
195 scp->cluster->reg_base + scp->data->host_to_scp_reg);
/linux-master/drivers/i2c/busses/
H A Di2c-sibyte.c20 void *reg_base; /* CSR base */ member in struct:i2c_algo_sibyte_data
24 #define SMB_CSR(a,r) ((long)(a->reg_base + r))
/linux-master/drivers/crypto/marvell/octeontx/
H A Dotx_cptvf.h81 void __iomem *reg_base; /* Register start address */ member in struct:otx_cptvf
/linux-master/arch/x86/platform/intel-quark/
H A Dimr.c43 int reg_base; member in struct:imr_device
112 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base;
144 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base;
589 idev->reg_base = QUARK_X1000_IMR_REGBASE;
/linux-master/drivers/spi/
H A Dspi-fsl-lib.h22 void __iomem *reg_base; member in struct:mpc8xxx_spi
/linux-master/drivers/media/platform/mediatek/vcodec/common/
H A Dmtk_vcodec_util.h65 void __iomem *mtk_vcodec_get_reg_addr(void __iomem **reg_base, unsigned int reg_idx);
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_wopcm.c203 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); local
207 !(reg_base & GUC_WOPCM_OFFSET_VALID))
210 *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;
/linux-master/drivers/irqchip/
H A Dirq-sunxi-nmi.c177 gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
178 if (IS_ERR(gc->reg_base)) {
180 ret = PTR_ERR(gc->reg_base);

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