/linux-master/arch/powerpc/mm/ptdump/ |
H A D | shared.c | 15 .val = 0, 20 .val = 0, 25 .val = _PAGE_EXEC, 30 .val = _PAGE_PRESENT, 35 .val = _PAGE_COHERENT, 40 .val = _PAGE_GUARDED, 45 .val = _PAGE_DIRTY, 50 .val = _PAGE_ACCESSED, 55 .val = _PAGE_WRITETHRU, 60 .val [all...] |
/linux-master/drivers/usb/phy/ |
H A D | phy-tegra-usb.c | 224 u32 val; local 227 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); 228 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); 229 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); 230 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); 232 val = readl_relaxed(base + TEGRA_USB_PORTSC1); 233 val &= ~TEGRA_PORTSC1_RWC_BITS; 234 val &= ~TEGRA_USB_PORTSC1_PTS(~0); 235 val |= TEGRA_USB_PORTSC1_PTS(pts_val); 236 writel_relaxed(val, bas 243 u32 val; local 330 u32 val; local 370 u32 val; local 420 u32 val; local 452 u32 val; local 487 u32 val; local 652 u32 val; local 717 u32 val; local 727 u32 val; local 738 u32 val; local 758 u32 val; local 769 u32 val; local 920 u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET; local 940 u32 val; local 1016 int err, val = 0; local [all...] |
/linux-master/arch/mips/txx9/generic/ |
H A D | mem_tx4927.c | 37 u64 val; local 48 val = __raw_readq(addr); 51 sdccr_ce = ((val & (1 << 10)) >> 10); 52 sdccr_bs = ((val & (1 << 8)) >> 8); 53 sdccr_rs = ((val & (3 << 5)) >> 5); 54 sdccr_cs = ((val & (7 << 2)) >> 2); 55 sdccr_mw = ((val & (1 << 0)) >> 0);
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/linux-master/arch/arm/mach-s3c/ |
H A D | wakeup-mask.c | 21 u32 val; local 23 val = __raw_readl(reg); 27 val |= mask->bit; 35 val &= ~mask->bit; 37 val |= mask->bit; 40 printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); 41 __raw_writel(val, reg);
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/linux-master/arch/arc/include/asm/ |
H A D | spinlock.h | 19 unsigned int val; local 22 "1: llock %[val], [%[slock]] \n" 23 " breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */ 27 : [val] "=&r" (val) 46 unsigned int val, got_it = 0; local 49 "1: llock %[val], [%[slock]] \n" 50 " breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */ 56 : [val] "=&r" (val), 81 unsigned int val; local 111 unsigned int val, got_it = 0; local 136 unsigned int val; local 169 unsigned int val, got_it = 0; local 195 unsigned int val; local 224 unsigned int val = __ARCH_SPIN_LOCK_LOCKED__; local 246 unsigned int val = __ARCH_SPIN_LOCK_LOCKED__; local 263 unsigned int val = __ARCH_SPIN_LOCK_UNLOCKED__; local [all...] |
/linux-master/tools/testing/selftests/powerpc/dscr/ |
H A D | dscr_sysfs_thread_test.c | 15 static int test_thread_dscr(unsigned long val) argument 22 if (val != cur_dscr) { 24 sched_getcpu(), val, cur_dscr); 28 if (val != cur_dscr_usr) { 30 sched_getcpu(), val, cur_dscr_usr); 36 static int check_cpu_dscr_thread(unsigned long val) argument 47 if (test_thread_dscr(val))
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/linux-master/tools/testing/selftests/bpf/progs/ |
H A D | bpf_iter_bpf_sk_storage_map.c | 25 __u32 *val = ctx->value; local 27 if (sk == NULL || val == NULL) 33 val_sum += *val; 35 *val += to_add_val; 44 __u32 *val = ctx->value; local 46 if (sk == NULL || val == NULL) 49 *(val + 1) = 0xdeadbeef;
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/linux-master/tools/testing/selftests/kvm/x86_64/ |
H A D | hwcr_msr_test.c | 18 uint64_t val = BIT_ULL(bit); local 22 r = _vcpu_set_msr(vcpu, MSR_K7_HWCR, val); 23 TEST_ASSERT(val & ~legal ? !r : r == 1, 25 val, val & ~legal ? "fail" : "succeed"); 28 TEST_ASSERT(actual == (val & valid), 30 bit, actual, (val & valid));
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/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a6xx.xml.h | 1377 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) argument 1379 assert(!(val & 0x3)); 1380 return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; 1384 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) argument 1386 assert(!(val & 0x3)); 1387 return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; 1391 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) argument 1393 assert(!(val & 0x3)); 1394 return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1398 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) argument 1407 A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) argument 1414 A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) argument 1442 A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) argument 1448 A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) argument 1517 A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val) argument 1523 A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val) argument 1531 A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val) argument 1537 A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val) argument 1545 A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val) argument 1551 A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val) argument 1559 A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val) argument 1565 A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val) argument 1573 A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val) argument 1579 A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val) argument 1587 A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val) argument 1593 A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val) argument 1611 A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val) argument 1619 A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val) argument 1627 A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val) argument 1635 A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val) argument 1643 A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val) argument 1651 A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) argument 1665 A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val) argument 1671 A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val) argument 1677 A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(uint32_t val) argument 1687 A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val) argument 1693 A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val) argument 1699 A7XX_CP_APERTURE_CNTL_CD_CONTEXT(uint32_t val) argument 2279 A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) argument 2285 A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) argument 2293 A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) argument 2299 A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) argument 2305 A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) argument 2313 A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) argument 2337 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) argument 2343 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) argument 2349 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) argument 2355 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) argument 2361 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) argument 2367 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) argument 2373 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) argument 2379 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) argument 2387 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) argument 2393 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) argument 2399 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) argument 2405 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) argument 2411 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) argument 2417 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) argument 2423 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) argument 2429 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) argument 2468 A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) argument 2497 A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) argument 2507 A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) argument 2613 A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) argument 2620 A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) argument 2631 A6XX_VSC_BIN_COUNT_NX(uint32_t val) argument 2637 A6XX_VSC_BIN_COUNT_NY(uint32_t val) argument 2647 A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) argument 2653 A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) argument 2659 A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) argument 2665 A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) argument 2713 A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) argument 2719 A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) argument 2727 A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) argument 2733 A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) argument 2741 A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) argument 2747 A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) argument 2763 A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) argument 2773 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) argument 2779 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) argument 2801 A6XX_GRAS_CL_VPORT_XOFFSET(float val) argument 2809 A6XX_GRAS_CL_VPORT_XSCALE(float val) argument 2817 A6XX_GRAS_CL_VPORT_YOFFSET(float val) argument 2825 A6XX_GRAS_CL_VPORT_YSCALE(float val) argument 2833 A6XX_GRAS_CL_VPORT_ZOFFSET(float val) argument 2841 A6XX_GRAS_CL_VPORT_ZSCALE(float val) argument 2851 A6XX_GRAS_CL_Z_CLAMP_MIN(float val) argument 2859 A6XX_GRAS_CL_Z_CLAMP_MAX(float val) argument 2870 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) argument 2878 A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) argument 2884 A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) argument 2893 A6XX_GRAS_SU_CNTL_UNK20(uint32_t val) argument 2901 A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) argument 2907 A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) argument 2915 A6XX_GRAS_SU_POINT_SIZE(float val) argument 2923 A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) argument 2931 A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) argument 2939 A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) argument 2947 A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) argument 2955 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) argument 2965 A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) argument 2972 A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) argument 2996 A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) argument 3002 A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) argument 3008 A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) argument 3014 A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) argument 3020 A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) argument 3027 A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) argument 3036 A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) argument 3043 A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) argument 3050 A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) argument 3057 A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) argument 3063 A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) argument 3072 A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) argument 3082 A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) argument 3095 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) argument 3101 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) argument 3107 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) argument 3113 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) argument 3119 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) argument 3125 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) argument 3131 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) argument 3137 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) argument 3145 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) argument 3151 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) argument 3157 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) argument 3163 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) argument 3169 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) argument 3175 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) argument 3181 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) argument 3187 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) argument 3201 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) argument 3207 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) argument 3215 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) argument 3221 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) argument 3231 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) argument 3237 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) argument 3245 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) argument 3251 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) argument 3259 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) argument 3265 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) argument 3273 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) argument 3279 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) argument 3305 A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) argument 3313 A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val) argument 3322 A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) argument 3330 A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) argument 3340 A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) argument 3347 A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) argument 3361 A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val) argument 3367 A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val) argument 3373 A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) argument 3385 A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val) argument 3399 A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) argument 3406 A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) argument 3413 A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) argument 3420 A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) argument 3427 A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) argument 3433 A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) argument 3439 A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) argument 3448 A6XX_GRAS_2D_SRC_TL_X(int32_t val) argument 3456 A6XX_GRAS_2D_SRC_BR_X(int32_t val) argument 3464 A6XX_GRAS_2D_SRC_TL_Y(int32_t val) argument 3472 A6XX_GRAS_2D_SRC_BR_Y(int32_t val) argument 3480 A6XX_GRAS_2D_DST_TL_X(uint32_t val) argument 3486 A6XX_GRAS_2D_DST_TL_Y(uint32_t val) argument 3494 A6XX_GRAS_2D_DST_BR_X(uint32_t val) argument 3500 A6XX_GRAS_2D_DST_BR_Y(uint32_t val) argument 3514 A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) argument 3520 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) argument 3528 A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) argument 3534 A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) argument 3556 A6XX_RB_BIN_CONTROL_BINW(uint32_t val) argument 3563 A6XX_RB_BIN_CONTROL_BINH(uint32_t val) argument 3570 A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) argument 3577 A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) argument 3583 A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) argument 3591 A7XX_RB_BIN_CONTROL_BINW(uint32_t val) argument 3598 A7XX_RB_BIN_CONTROL_BINH(uint32_t val) argument 3605 A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) argument 3612 A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) argument 3620 A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) argument 3628 A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) argument 3634 A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) argument 3640 A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) argument 3649 A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) argument 3659 A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) argument 3665 A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) argument 3678 A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) argument 3688 A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) argument 3701 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) argument 3707 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) argument 3713 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) argument 3719 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) argument 3725 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) argument 3731 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) argument 3737 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) argument 3743 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) argument 3751 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) argument 3757 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) argument 3763 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) argument 3769 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) argument 3775 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) argument 3781 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) argument 3787 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) argument 3793 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) argument 3807 A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) argument 3820 A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) argument 3837 A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) argument 3845 A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) argument 3851 A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) argument 3857 A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) argument 3863 A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) argument 3869 A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) argument 3875 A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) argument 3881 A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) argument 3887 A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) argument 3895 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) argument 3901 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) argument 3907 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) argument 3913 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) argument 3919 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) argument 3925 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) argument 3931 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) argument 3937 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) argument 3981 A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) argument 3987 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) argument 3995 A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) argument 4001 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) argument 4007 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) argument 4013 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) argument 4019 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) argument 4025 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) argument 4033 A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) argument 4039 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) argument 4046 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument 4054 A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) argument 4060 A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) argument 4068 A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument 4076 A6XX_RB_MRT_PITCH(uint32_t val) argument 4085 A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) argument 4098 A6XX_RB_BLEND_RED_F32(float val) argument 4106 A6XX_RB_BLEND_GREEN_F32(float val) argument 4114 A6XX_RB_BLEND_BLUE_F32(float val) argument 4122 A6XX_RB_BLEND_ALPHA_F32(float val) argument 4130 A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) argument 4137 A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) argument 4145 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) argument 4155 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) argument 4163 A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) argument 4173 A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) argument 4187 A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) argument 4193 A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) argument 4201 A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) argument 4207 A7XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) argument 4213 A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val) argument 4222 A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) argument 4231 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) argument 4244 A6XX_RB_Z_BOUNDS_MIN(float val) argument 4252 A6XX_RB_Z_BOUNDS_MAX(float val) argument 4263 A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) argument 4269 A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) argument 4275 A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) argument 4281 A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) argument 4287 A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) argument 4293 A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) argument 4299 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) argument 4305 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) argument 4322 A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val) argument 4330 A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) argument 4339 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) argument 4352 A6XX_RB_STENCILREF_REF(uint32_t val) argument 4358 A6XX_RB_STENCILREF_BFREF(uint32_t val) argument 4366 A6XX_RB_STENCILMASK_MASK(uint32_t val) argument 4372 A6XX_RB_STENCILMASK_BFMASK(uint32_t val) argument 4380 A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) argument 4386 A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) argument 4394 A6XX_RB_WINDOW_OFFSET_X(uint32_t val) argument 4400 A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) argument 4417 A6XX_RB_Z_CLAMP_MIN(float val) argument 4425 A6XX_RB_Z_CLAMP_MAX(float val) argument 4433 A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) argument 4439 A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) argument 4447 A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) argument 4453 A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) argument 4461 A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) argument 4467 A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) argument 4475 A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) argument 4482 A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) argument 4491 A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) argument 4497 A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) argument 4505 A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) argument 4515 A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) argument 4522 A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) argument 4528 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument 4534 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) argument 4545 A6XX_RB_BLIT_DST_PITCH(uint32_t val) argument 4554 A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) argument 4565 A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) argument 4572 A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) argument 4593 A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) argument 4599 A6XX_RB_BLIT_INFO_LAST(uint32_t val) argument 4605 A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) argument 4616 A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(uint32_t val) argument 4622 A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(uint32_t val) argument 4628 A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) argument 4634 A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(uint32_t val) argument 4641 A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) argument 4647 A7XX_RB_CCU_CNTL2_COLOR_OFFSET(uint32_t val) argument 4660 A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) argument 4667 A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) argument 4682 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) argument 4689 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) argument 4695 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) argument 4708 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) argument 4715 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) argument 4734 A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) argument 4741 A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) argument 4748 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) argument 4755 A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) argument 4762 A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) argument 4768 A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) argument 4774 A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) argument 4785 A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) argument 4791 A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) argument 4797 A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument 4805 A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) argument 4818 A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) argument 4829 A6XX_RB_2D_DST_PITCH(uint32_t val) argument 4840 A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) argument 4853 A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) argument 4864 A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) argument 4891 A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val) argument 4897 A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) argument 4903 A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) argument 4909 A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) argument 4916 A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) argument 4922 A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) argument 4936 A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) argument 4944 A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) argument 4951 A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) argument 4981 A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) argument 4989 A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) argument 4995 A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) argument 5001 A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) argument 5009 A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) argument 5015 A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) argument 5021 A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) argument 5029 A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) argument 5035 A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) argument 5041 A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) argument 5049 A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) argument 5055 A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) argument 5061 A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) argument 5069 A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) argument 5075 A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) argument 5081 A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) argument 5089 A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) argument 5095 A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) argument 5101 A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) argument 5109 A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) argument 5115 A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) argument 5121 A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) argument 5129 A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) argument 5135 A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) argument 5141 A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) argument 5149 A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) argument 5155 A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) argument 5161 A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) argument 5169 A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) argument 5175 A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) argument 5181 A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) argument 5189 A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) argument 5195 A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) argument 5201 A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) argument 5209 A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) argument 5215 A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) argument 5221 A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) argument 5233 A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) argument 5247 A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) argument 5253 A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) argument 5260 A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) argument 5273 A7XX_VPC_MULTIVIEW_CNTL_VIEWS(uint32_t val) argument 5297 A6XX_VPC_SO_CNTL_ADDR(uint32_t val) argument 5306 A6XX_VPC_SO_PROG_A_BUF(uint32_t val) argument 5312 A6XX_VPC_SO_PROG_A_OFF(uint32_t val) argument 5320 A6XX_VPC_SO_PROG_B_BUF(uint32_t val) argument 5326 A6XX_VPC_SO_PROG_B_OFF(uint32_t val) argument 5355 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) argument 5361 A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) argument 5367 A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) argument 5373 A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) argument 5381 A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) argument 5387 A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) argument 5393 A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) argument 5399 A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) argument 5407 A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) argument 5413 A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) argument 5419 A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) argument 5425 A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) argument 5433 A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) argument 5439 A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) argument 5446 A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) argument 5454 A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) argument 5460 A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) argument 5466 A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) argument 5472 A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) argument 5478 A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) argument 5489 A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val) argument 5497 A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) argument 5505 A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(uint32_t val) argument 5513 A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) argument 5535 A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) argument 5544 A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) argument 5550 A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) argument 5567 A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) argument 5578 A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) argument 5586 A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) argument 5594 A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) argument 5600 A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) argument 5610 A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) argument 5618 A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) argument 5626 A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) argument 5635 A7XX_PC_RASTER_CNTL_STREAM(uint32_t val) argument 5644 A7XX_PC_RASTER_CNTL_V2_STREAM(uint32_t val) argument 5659 A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) argument 5669 A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) argument 5678 A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) argument 5688 A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) argument 5697 A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) argument 5707 A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) argument 5716 A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) argument 5726 A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) argument 5735 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) argument 5741 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) argument 5748 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) argument 5757 A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) argument 5767 A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) argument 5777 A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) argument 5783 A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) argument 5805 A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) argument 5811 A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) argument 5817 A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) argument 5823 A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) argument 5829 A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) argument 5843 A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) argument 5849 A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) argument 5855 A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) argument 5878 A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) argument 5884 A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) argument 5892 A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) argument 5898 A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) argument 5904 A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) argument 5910 A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) argument 5918 A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) argument 5924 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) argument 5932 A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) argument 5938 A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) argument 5944 A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) argument 5950 A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) argument 5958 A6XX_VFD_CONTROL_4_UNK0(uint32_t val) argument 5966 A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) argument 5972 A6XX_VFD_CONTROL_5_UNK8(uint32_t val) argument 5983 A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) argument 5993 A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) argument 6019 A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) argument 6025 A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) argument 6032 A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) argument 6038 A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) argument 6052 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) argument 6058 A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) argument 6076 A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 6082 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 6088 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 6095 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) argument 6107 A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) argument 6113 A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) argument 6123 A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) argument 6129 A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) argument 6135 A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) argument 6141 A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) argument 6151 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) argument 6157 A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) argument 6163 A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) argument 6169 A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) argument 6181 A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) argument 6188 A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) argument 6198 A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) argument 6215 A6XX_SP_VS_CONFIG_NTEX(uint32_t val) argument 6221 A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) argument 6227 A6XX_SP_VS_CONFIG_NIBO(uint32_t val) argument 6237 A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) argument 6248 A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 6254 A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 6260 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 6267 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) argument 6284 A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) argument 6291 A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) argument 6301 A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) argument 6318 A6XX_SP_HS_CONFIG_NTEX(uint32_t val) argument 6324 A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) argument 6330 A6XX_SP_HS_CONFIG_NIBO(uint32_t val) argument 6340 A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) argument 6351 A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 6357 A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 6363 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 6370 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) argument 6381 A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) argument 6387 A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) argument 6397 A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) argument 6403 A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) argument 6409 A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) argument 6415 A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) argument 6425 A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) argument 6431 A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) argument 6437 A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) argument 6443 A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) argument 6455 A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) argument 6462 A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) argument 6472 A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) argument 6489 A6XX_SP_DS_CONFIG_NTEX(uint32_t val) argument 6495 A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) argument 6501 A6XX_SP_DS_CONFIG_NIBO(uint32_t val) argument 6511 A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) argument 6522 A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 6528 A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 6534 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 6541 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) argument 6554 A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) argument 6560 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) argument 6570 A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) argument 6576 A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) argument 6582 A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) argument 6588 A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) argument 6598 A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) argument 6604 A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) argument 6610 A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) argument 6616 A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) argument 6628 A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) argument 6635 A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) argument 6645 A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) argument 6662 A6XX_SP_GS_CONFIG_NTEX(uint32_t val) argument 6668 A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) argument 6674 A6XX_SP_GS_CONFIG_NIBO(uint32_t val) argument 6684 A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) argument 6711 A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 6717 A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 6723 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 6730 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) argument 6736 A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) argument 6759 A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) argument 6766 A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) argument 6776 A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) argument 6786 A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) argument 6807 A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) argument 6813 A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) argument 6819 A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) argument 6825 A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) argument 6831 A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) argument 6837 A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) argument 6843 A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) argument 6849 A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) argument 6858 A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) argument 6864 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) argument 6870 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) argument 6878 A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) argument 6888 A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) argument 6899 A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) argument 6910 A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) argument 6919 A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(uint32_t val) argument 6925 A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(uint32_t val) argument 6935 A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) argument 6941 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) argument 6947 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) argument 6953 A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) argument 6959 A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) argument 6968 A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) argument 6978 A7XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) argument 6984 A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) argument 6990 A7XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) argument 6996 A7XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) argument 7002 A7XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) argument 7010 A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) argument 7020 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) argument 7026 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) argument 7038 A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) argument 7047 A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 7053 A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 7059 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 7066 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) argument 7072 A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) argument 7084 A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) argument 7100 A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) argument 7107 A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) argument 7117 A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) argument 7134 A6XX_SP_CS_CONFIG_NTEX(uint32_t val) argument 7140 A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) argument 7146 A6XX_SP_CS_CONFIG_NIBO(uint32_t val) argument 7156 A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) argument 7169 A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) argument 7175 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) argument 7181 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) argument 7187 A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) argument 7195 A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) argument 7202 A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) argument 7211 A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) argument 7217 A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) argument 7237 A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) argument 7243 A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) argument 7254 A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) argument 7260 A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) argument 7278 A7XX_SP_PS_ALIASED_COMPONENTS_RT0(uint32_t val) argument 7284 A7XX_SP_PS_ALIASED_COMPONENTS_RT1(uint32_t val) argument 7290 A7XX_SP_PS_ALIASED_COMPONENTS_RT2(uint32_t val) argument 7296 A7XX_SP_PS_ALIASED_COMPONENTS_RT3(uint32_t val) argument 7302 A7XX_SP_PS_ALIASED_COMPONENTS_RT4(uint32_t val) argument 7308 A7XX_SP_PS_ALIASED_COMPONENTS_RT5(uint32_t val) argument 7314 A7XX_SP_PS_ALIASED_COMPONENTS_RT6(uint32_t val) argument 7320 A7XX_SP_PS_ALIASED_COMPONENTS_RT7(uint32_t val) argument 7331 A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) argument 7349 A6XX_SP_FS_CONFIG_NTEX(uint32_t val) argument 7355 A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) argument 7361 A6XX_SP_FS_CONFIG_NIBO(uint32_t val) argument 7373 A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) argument 7379 A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) argument 7390 A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) argument 7396 A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) argument 7414 A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) argument 7421 A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) argument 7432 A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) argument 7439 A7XX_SP_2D_DST_FORMAT_MASK(uint32_t val) argument 7484 A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val) argument 7490 A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val) argument 7496 A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val) argument 7502 A7XX_SP_READ_SEL_USPTP(uint32_t val) argument 7508 A7XX_SP_READ_SEL_SPTP(uint32_t val) argument 7534 A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) argument 7540 A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) argument 7548 A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) argument 7563 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) argument 7569 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) argument 7575 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) argument 7581 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) argument 7587 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) argument 7593 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) argument 7599 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) argument 7605 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) argument 7613 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) argument 7619 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) argument 7625 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) argument 7631 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) argument 7637 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) argument 7643 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) argument 7649 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) argument 7655 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) argument 7663 A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) argument 7669 A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) argument 7677 A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) argument 7683 A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) argument 7693 A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) argument 7699 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) argument 7705 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument 7713 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) argument 7726 A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) argument 7735 A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) argument 7741 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) argument 7751 A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) argument 7757 A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) argument 7766 A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) argument 7772 A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) argument 7778 A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument 7786 A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) argument 7799 A7XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) argument 7808 A7XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) argument 7814 A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) argument 7824 A7XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) argument 7830 A7XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) argument 7841 A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) argument 7854 A7XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) argument 7867 A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) argument 7878 A7XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) argument 7895 A6XX_SP_WINDOW_OFFSET_X(uint32_t val) argument 7901 A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) argument 7917 A7XX_SP_PS_2D_WINDOW_OFFSET_X(uint32_t val) argument 7923 A7XX_SP_PS_2D_WINDOW_OFFSET_Y(uint32_t val) argument 7933 A7XX_SP_WINDOW_OFFSET_X(uint32_t val) argument 7939 A7XX_SP_WINDOW_OFFSET_Y(uint32_t val) argument 7954 A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) argument 7961 A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) argument 7967 A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) argument 7999 A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) argument 8010 A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) argument 8021 A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) argument 8032 A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) argument 8043 A7XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) argument 8054 A7XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) argument 8065 A7XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) argument 8076 A7XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) argument 8094 A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(uint32_t val) argument 8110 A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) argument 8117 A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) argument 8127 A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) argument 8135 A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) argument 8141 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) argument 8147 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) argument 8153 A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) argument 8161 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) argument 8167 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) argument 8173 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) argument 8179 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) argument 8187 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) argument 8193 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) argument 8199 A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) argument 8205 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) argument 8213 A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) argument 8219 A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) argument 8227 A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) argument 8238 A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) argument 8245 A7XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) argument 8253 A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) argument 8261 A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) argument 8267 A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) argument 8273 A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) argument 8279 A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) argument 8287 A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) argument 8293 A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) argument 8299 A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) argument 8305 A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) argument 8313 A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) argument 8319 A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) argument 8325 A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) argument 8331 A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) argument 8339 A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) argument 8345 A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) argument 8353 A7XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) argument 8364 A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) argument 8370 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) argument 8376 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) argument 8382 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) argument 8390 A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) argument 8398 A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) argument 8406 A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) argument 8414 A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) argument 8422 A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) argument 8430 A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) argument 8438 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) argument 8444 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) argument 8450 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) argument 8456 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) argument 8464 A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) argument 8471 A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) argument 8486 A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) argument 8492 A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) argument 8498 A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) argument 8504 A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) argument 8512 A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) argument 8520 A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) argument 8528 A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) argument 8536 A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) argument 8544 A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) argument 8552 A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) argument 8566 A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) argument 8572 A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) argument 8581 A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val) argument 8589 A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(uint32_t val) argument 8595 A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(uint32_t val) argument 8601 A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(uint32_t val) argument 8617 A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) argument 8623 A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) argument 8632 A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) argument 8642 A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) argument 8650 A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) argument 8658 A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) argument 8664 A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) argument 8682 A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) argument 8688 A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) argument 8704 A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) argument 8710 A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) argument 8718 A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) argument 8729 A7XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) argument 8747 A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) argument 8753 A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) argument 8762 A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) argument 8768 A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) argument 8798 A6XX_CP_EVENT_START_STATE_ID(uint32_t val) argument 8806 A6XX_CP_EVENT_END_STATE_ID(uint32_t val) argument 8814 A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) argument 8822 A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) argument 8831 A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) argument 8837 A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) argument 8843 A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) argument 8849 A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) argument 8855 A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) argument 8861 A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) argument 8867 A6XX_TEX_SAMP_0_LOD_BIAS(float val) argument 8876 A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) argument 8885 A6XX_TEX_SAMP_1_MAX_LOD(float val) argument 8891 A6XX_TEX_SAMP_1_MIN_LOD(float val) argument 8899 A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) argument 8906 A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) argument 8916 A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) argument 8923 A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) argument 8929 A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) argument 8935 A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) argument 8941 A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) argument 8947 A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) argument 8955 A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) argument 8961 A6XX_TEX_CONST_0_FMT(enum a6xx_format val) argument 8967 A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) argument 8975 A6XX_TEX_CONST_1_WIDTH(uint32_t val) argument 8981 A6XX_TEX_CONST_1_HEIGHT(uint32_t val) argument 8989 A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val) argument 8995 A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val) argument 9001 A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) argument 9007 A6XX_TEX_CONST_2_PITCH(uint32_t val) argument 9013 A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) argument 9021 A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) argument 9028 A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) argument 9039 A6XX_TEX_CONST_4_BASE_LO(uint32_t val) argument 9048 A6XX_TEX_CONST_5_BASE_HI(uint32_t val) argument 9054 A6XX_TEX_CONST_5_DEPTH(uint32_t val) argument 9062 A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val) argument 9068 A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) argument 9076 A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) argument 9085 A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) argument 9093 A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) argument 9102 A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) argument 9109 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) argument 9115 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) argument 9133 A6XX_UBO_0_BASE_LO(uint32_t val) argument 9141 A6XX_UBO_1_BASE_HI(uint32_t val) argument 9147 A6XX_UBO_1_SIZE(uint32_t val) argument 9209 A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) argument 9215 A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) argument 9229 A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) argument 9235 A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) argument 9241 A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) argument 9249 A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) argument 9273 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) argument 9279 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) argument 9285 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) argument 9291 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) argument 9297 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) argument 9303 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) argument 9309 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) argument 9315 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) argument 9323 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) argument 9329 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) argument 9335 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) argument 9341 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) argument 9347 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) argument 9353 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) argument 9359 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) argument 9365 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) argument [all...] |
H A D | a2xx.xml.h | 1177 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1179 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 1183 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1185 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 1189 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1191 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 1195 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1197 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 1201 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1203 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIF 1207 A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1213 A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1219 A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1225 A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1231 A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1237 A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument 1245 A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) argument 1251 A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) argument 1362 A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT(enum perf_mode_cnt val) argument 1376 A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) argument 1403 A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) argument 1413 A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) argument 1422 A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) argument 1448 A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) argument 1455 A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) argument 1486 A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) argument 1495 A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) argument 1501 A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) argument 1511 A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) argument 1517 A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) argument 1579 A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) argument 1590 A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) argument 1600 A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) argument 1607 A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) argument 1613 A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) argument 1630 A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) argument 1636 A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) argument 1644 A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) argument 1650 A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) argument 1657 A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) argument 1663 A2XX_RB_COLOR_INFO_SWAP(uint32_t val) argument 1669 A2XX_RB_COLOR_INFO_BASE(uint32_t val) argument 1678 A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) argument 1684 A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) argument 1698 A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) argument 1704 A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) argument 1713 A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) argument 1719 A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) argument 1727 A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) argument 1733 A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) argument 1743 A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) argument 1749 A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) argument 1758 A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) argument 1764 A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) argument 1796 A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) argument 1802 A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) argument 1808 A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) argument 1816 A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) argument 1822 A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) argument 1828 A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) argument 1836 A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) argument 1842 A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) argument 1848 A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) argument 1858 A2XX_PA_CL_VPORT_XSCALE(float val) argument 1866 A2XX_PA_CL_VPORT_XOFFSET(float val) argument 1874 A2XX_PA_CL_VPORT_YSCALE(float val) argument 1882 A2XX_PA_CL_VPORT_YOFFSET(float val) argument 1890 A2XX_PA_CL_VPORT_ZSCALE(float val) argument 1898 A2XX_PA_CL_VPORT_ZOFFSET(float val) argument 1906 A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) argument 1912 A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) argument 1922 A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) argument 1928 A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) argument 1934 A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) argument 1945 A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) argument 1951 A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) argument 1962 A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) argument 1968 A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) argument 1976 A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) argument 1982 A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) argument 1988 A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) argument 1994 A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) argument 2000 A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) argument 2006 A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) argument 2012 A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) argument 2018 A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) argument 2026 A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) argument 2032 A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) argument 2038 A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) argument 2044 A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) argument 2050 A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) argument 2056 A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) argument 2062 A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) argument 2068 A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) argument 2076 A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) argument 2082 A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) argument 2090 A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) argument 2096 A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) argument 2106 A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) argument 2112 A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) argument 2118 A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) argument 2124 A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) argument 2133 A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) argument 2147 A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) argument 2154 A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) argument 2160 A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) argument 2166 A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) argument 2172 A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) argument 2178 A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) argument 2184 A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) argument 2190 A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) argument 2196 A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) argument 2204 A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) argument 2210 A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) argument 2216 A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) argument 2222 A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) argument 2228 A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) argument 2234 A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) argument 2244 A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) argument 2255 A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) argument 2261 A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) argument 2267 A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) argument 2274 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) argument 2280 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) argument 2286 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) argument 2292 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) argument 2300 A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) argument 2306 A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) argument 2312 A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) argument 2322 A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) argument 2338 A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) argument 2344 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) argument 2350 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) argument 2386 A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) argument 2392 A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) argument 2398 A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) argument 2406 A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) argument 2418 A2XX_CLEAR_COLOR_RED(uint32_t val) argument 2424 A2XX_CLEAR_COLOR_GREEN(uint32_t val) argument 2430 A2XX_CLEAR_COLOR_BLUE(uint32_t val) argument 2436 A2XX_CLEAR_COLOR_ALPHA(uint32_t val) argument 2446 A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) argument 2452 A2XX_PA_SU_POINT_SIZE_WIDTH(float val) argument 2460 A2XX_PA_SU_POINT_MINMAX_MIN(float val) argument 2466 A2XX_PA_SU_POINT_MINMAX_MAX(float val) argument 2474 A2XX_PA_SU_LINE_CNTL_WIDTH(float val) argument 2482 A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) argument 2488 A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) argument 2494 A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) argument 2500 A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) argument 2509 A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) argument 2520 A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) argument 2531 A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) argument 2537 A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) argument 2545 A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) argument 2551 A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) argument 2557 A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) argument 2565 A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) argument 2573 A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) argument 2581 A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) argument 2589 A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) argument 2597 A2XX_SQ_VS_CONST_BASE(uint32_t val) argument 2603 A2XX_SQ_VS_CONST_SIZE(uint32_t val) argument 2611 A2XX_SQ_PS_CONST_BASE(uint32_t val) argument 2617 A2XX_SQ_PS_CONST_SIZE(uint32_t val) argument 2631 A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) argument 2639 A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) argument 2647 A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) argument 2654 A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) argument 2664 A2XX_RB_COPY_DEST_PITCH(uint32_t val) argument 2673 A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) argument 2680 A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) argument 2686 A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) argument 2692 A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) argument 2698 A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) argument 2710 A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) argument 2716 A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) argument 2990 A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) argument 2996 A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) argument 3002 A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) argument 3008 A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) argument 3014 A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) argument 3020 A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) argument 3026 A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) argument 3032 A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) argument 3038 A2XX_SQ_TEX_0_PITCH(uint32_t val) argument 3048 A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) argument 3054 A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) argument 3060 A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) argument 3067 A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) argument 3073 A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) argument 3082 A2XX_SQ_TEX_2_WIDTH(uint32_t val) argument 3088 A2XX_SQ_TEX_2_HEIGHT(uint32_t val) argument 3094 A2XX_SQ_TEX_2_DEPTH(uint32_t val) argument 3102 A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) argument 3108 A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) argument 3114 A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) argument 3120 A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) argument 3126 A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) argument 3132 A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val) argument 3138 A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) argument 3144 A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) argument 3150 A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) argument 3156 A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) argument 3162 A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) argument 3170 A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) argument 3176 A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) argument 3182 A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) argument 3188 A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) argument 3196 A2XX_SQ_TEX_4_LOD_BIAS(float val) argument 3202 A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) argument 3208 A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) argument 3216 A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) argument 3223 A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) argument 3229 A2XX_SQ_TEX_5_ANISO_BIAS(float val) argument 3235 A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) argument 3242 A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) argument [all...] |
H A D | a4xx.xml.h | 850 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) argument 852 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 909 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) argument 911 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 915 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) argument 917 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 931 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) argument 933 assert(!(val & 0x1f)); 934 return (((val >> 5)) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 938 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) argument 953 A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) argument 961 A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val) argument 970 A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) argument 989 A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) argument 995 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) argument 1003 A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) argument 1009 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) argument 1015 A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) argument 1021 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument 1028 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) argument 1039 A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) argument 1047 A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) argument 1053 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) argument 1059 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) argument 1065 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) argument 1071 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) argument 1077 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) argument 1085 A4XX_RB_BLEND_RED_UINT(uint32_t val) argument 1091 A4XX_RB_BLEND_RED_SINT(uint32_t val) argument 1097 A4XX_RB_BLEND_RED_FLOAT(float val) argument 1105 A4XX_RB_BLEND_RED_F32(float val) argument 1113 A4XX_RB_BLEND_GREEN_UINT(uint32_t val) argument 1119 A4XX_RB_BLEND_GREEN_SINT(uint32_t val) argument 1125 A4XX_RB_BLEND_GREEN_FLOAT(float val) argument 1133 A4XX_RB_BLEND_GREEN_F32(float val) argument 1141 A4XX_RB_BLEND_BLUE_UINT(uint32_t val) argument 1147 A4XX_RB_BLEND_BLUE_SINT(uint32_t val) argument 1153 A4XX_RB_BLEND_BLUE_FLOAT(float val) argument 1161 A4XX_RB_BLEND_BLUE_F32(float val) argument 1169 A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) argument 1175 A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) argument 1181 A4XX_RB_BLEND_ALPHA_FLOAT(float val) argument 1189 A4XX_RB_BLEND_ALPHA_F32(float val) argument 1197 A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) argument 1204 A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) argument 1212 A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) argument 1219 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) argument 1228 A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) argument 1237 A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) argument 1243 A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) argument 1249 A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) argument 1255 A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) argument 1261 A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) argument 1267 A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) argument 1273 A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) argument 1279 A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) argument 1287 A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) argument 1293 A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) argument 1299 A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) argument 1305 A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) argument 1314 A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) argument 1323 A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) argument 1332 A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) argument 1338 A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) argument 1344 A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) argument 1350 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) argument 1356 A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) argument 1362 A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) argument 1370 A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) argument 1382 A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) argument 1396 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) argument 1402 A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) argument 1411 A4XX_RB_DEPTH_PITCH(uint32_t val) argument 1420 A4XX_RB_DEPTH_PITCH2(uint32_t val) argument 1432 A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) argument 1438 A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) argument 1444 A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) argument 1450 A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) argument 1456 A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) argument 1462 A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) argument 1468 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) argument 1474 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) argument 1486 A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) argument 1495 A4XX_RB_STENCIL_PITCH(uint32_t val) argument 1504 A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) argument 1510 A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) argument 1516 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) argument 1524 A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) argument 1530 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) argument 1536 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) argument 1545 A4XX_RB_BIN_OFFSET_X(uint32_t val) argument 1551 A4XX_RB_BIN_OFFSET_Y(uint32_t val) argument 2219 A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) argument 2225 A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) argument 2309 A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 2317 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 2323 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 2329 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) argument 2335 A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) argument 2345 A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) argument 2351 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) argument 2359 A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) argument 2365 A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) argument 2371 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) argument 2381 A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) argument 2387 A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) argument 2393 A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) argument 2399 A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) argument 2409 A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) argument 2415 A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) argument 2421 A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) argument 2427 A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) argument 2435 A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) argument 2441 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) argument 2457 A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 2465 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 2471 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 2477 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) argument 2483 A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) argument 2493 A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) argument 2504 A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) argument 2510 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) argument 2526 A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) argument 2533 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) argument 2539 A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) argument 2549 A4XX_SP_FS_MRT_REG_REGID(uint32_t val) argument 2558 A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) argument 2567 A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument 2575 A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument 2581 A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument 2587 A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) argument 2593 A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) argument 2615 A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) argument 2621 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) argument 2637 A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) argument 2643 A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) argument 2653 A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) argument 2659 A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) argument 2665 A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) argument 2671 A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) argument 2681 A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) argument 2687 A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) argument 2693 A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) argument 2699 A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) argument 2707 A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) argument 2713 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) argument 2729 A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) argument 2735 A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) argument 2741 A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) argument 2751 A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) argument 2757 A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) argument 2763 A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) argument 2769 A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) argument 2779 A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) argument 2785 A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) argument 2791 A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) argument 2797 A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) argument 2805 A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) argument 2811 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) argument 2841 A4XX_VPC_ATTR_TOTALATTR(uint32_t val) argument 2848 A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) argument 2857 A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) argument 2863 A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) argument 2869 A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) argument 2887 A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) argument 2894 A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) argument 2911 A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) argument 2917 A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) argument 2923 A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) argument 2929 A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) argument 2973 A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) argument 2979 A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) argument 2985 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) argument 2991 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) argument 2999 A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) argument 3005 A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) argument 3011 A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) argument 3021 A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) argument 3027 A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) argument 3033 A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) argument 3047 A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) argument 3053 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) argument 3065 A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) argument 3073 A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) argument 3083 A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) argument 3090 A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) argument 3096 A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) argument 3103 A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) argument 3109 A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) argument 3141 A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) argument 3147 A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) argument 3153 A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) argument 3159 A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) argument 3175 A4XX_TPL1_TP_FS_TEX_COUNT_FS(uint32_t val) argument 3181 A4XX_TPL1_TP_FS_TEX_COUNT_CS(uint32_t val) argument 3227 A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) argument 3233 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) argument 3241 A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) argument 3249 A4XX_GRAS_CL_VPORT_XSCALE_0(float val) argument 3257 A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) argument 3265 A4XX_GRAS_CL_VPORT_YSCALE_0(float val) argument 3273 A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) argument 3281 A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) argument 3289 A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) argument 3295 A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) argument 3303 A4XX_GRAS_SU_POINT_SIZE(float val) argument 3315 A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) argument 3323 A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) argument 3331 A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) argument 3339 A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) argument 3350 A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) argument 3361 A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) argument 3367 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) argument 3374 A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) argument 3383 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) argument 3389 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) argument 3398 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) argument 3404 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) argument 3413 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) argument 3419 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) argument 3428 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) argument 3434 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) argument 3443 A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) argument 3449 A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) argument 3458 A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) argument 3464 A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) argument 3526 A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) argument 3536 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) argument 3548 A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) argument 3556 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) argument 3562 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) argument 3570 A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) argument 3576 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) argument 3582 A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) argument 3588 A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) argument 3596 A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) argument 3602 A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) argument 3608 A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) argument 3614 A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) argument 3622 A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) argument 3628 A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) argument 3636 A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument 3642 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) argument 3650 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) argument 3656 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument 3664 A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument 3670 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) argument 3678 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) argument 3684 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument 3692 A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument 3698 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) argument 3706 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) argument 3712 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument 3720 A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument 3726 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) argument 3734 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) argument 3740 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument 3748 A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument 3754 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) argument 3762 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) argument 3768 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument 3776 A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument 3782 A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) argument 3790 A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) argument 3796 A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument 3804 A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) argument 3810 A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) argument 3816 A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) argument 3822 A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) argument 3830 A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) argument 3840 A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) argument 3850 A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) argument 3860 A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) argument 3866 A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val) argument 3872 A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) argument 3880 A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val) argument 3886 A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val) argument 3894 A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val) argument 3900 A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val) argument 3914 A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val) argument 3949 A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) argument 3955 A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) argument 3963 A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) argument 3974 A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) argument 3980 A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) argument 3991 A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) argument 3997 A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) argument 4003 A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) argument 4012 A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) argument 4018 A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) argument 4126 A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) argument 4132 A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) argument 4138 A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) argument 4144 A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) argument 4150 A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) argument 4156 A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) argument 4162 A4XX_TEX_SAMP_0_LOD_BIAS(float val) argument 4170 A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) argument 4179 A4XX_TEX_SAMP_1_MAX_LOD(float val) argument 4185 A4XX_TEX_SAMP_1_MIN_LOD(float val) argument 4195 A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) argument 4201 A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) argument 4207 A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) argument 4213 A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) argument 4219 A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) argument 4225 A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) argument 4231 A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) argument 4239 A4XX_TEX_CONST_1_HEIGHT(uint32_t val) argument 4245 A4XX_TEX_CONST_1_WIDTH(uint32_t val) argument 4253 A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val) argument 4260 A4XX_TEX_CONST_2_PITCH(uint32_t val) argument 4266 A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) argument 4274 A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) argument 4281 A4XX_TEX_CONST_3_DEPTH(uint32_t val) argument 4289 A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) argument 4296 A4XX_TEX_CONST_4_BASE(uint32_t val) argument 4311 A4XX_SSBO_0_0_BASE(uint32_t val) argument 4320 A4XX_SSBO_0_1_PITCH(uint32_t val) argument 4328 A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) argument 4337 A4XX_SSBO_0_3_CPP(uint32_t val) argument 4345 A4XX_SSBO_1_0_CPP(uint32_t val) argument 4351 A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) argument 4357 A4XX_SSBO_1_0_WIDTH(uint32_t val) argument 4365 A4XX_SSBO_1_1_HEIGHT(uint32_t val) argument 4371 A4XX_SSBO_1_1_DEPTH(uint32_t val) argument [all...] |
/linux-master/arch/powerpc/lib/ |
H A D | qspinlock.c | 105 static inline int decode_tail_cpu(u32 val) argument 107 return (val >> _Q_TAIL_CPU_OFFSET) - 1; 110 static inline int get_owner_cpu(u32 val) argument 112 return (val & _Q_OWNER_CPU_MASK) >> _Q_OWNER_CPU_OFFSET; 145 : "r" (&lock->val), "r"(tail), "r" (newval), 175 : "r" (&lock->val), "r" (tail), "r"(_Q_TAIL_CPU_MASK) 191 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL) 207 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL) 229 : "r" (&lock->val), "r"(old), "r" (new) 235 static __always_inline void seen_sleepy_owner(struct qspinlock *lock, u32 val) argument 284 __yield_to_locked_owner(struct qspinlock *lock, u32 val, bool paravirt, bool mustq) argument 337 yield_to_locked_owner(struct qspinlock *lock, u32 val, bool paravirt) argument 343 yield_head_to_locked_owner(struct qspinlock *lock, u32 val, bool paravirt) argument 353 propagate_sleepy(struct qnode *node, u32 val, bool paravirt) argument 392 u32 val = READ_ONCE(lock->val); local 442 steal_break(u32 val, int iters, bool paravirt, bool sleepy) argument 461 u32 val; local 530 u32 val, old, tail; local 733 steal_spins_set(void *data, u64 val) argument 768 steal_spins_get(void *data, u64 *val) argument 777 remote_steal_spins_set(void *data, u64 val) argument 784 remote_steal_spins_get(void *data, u64 *val) argument 793 head_spins_set(void *data, u64 val) argument 800 head_spins_get(void *data, u64 *val) argument 809 pv_yield_owner_set(void *data, u64 val) argument 816 pv_yield_owner_get(void *data, u64 *val) argument 825 pv_yield_allow_steal_set(void *data, u64 val) argument 832 pv_yield_allow_steal_get(void *data, u64 *val) argument 841 pv_spin_on_preempted_owner_set(void *data, u64 val) argument 848 pv_spin_on_preempted_owner_get(void *data, u64 *val) argument 857 pv_sleepy_lock_set(void *data, u64 val) argument 864 pv_sleepy_lock_get(void *data, u64 *val) argument 873 pv_sleepy_lock_sticky_set(void *data, u64 val) argument 880 pv_sleepy_lock_sticky_get(void *data, u64 *val) argument 889 pv_sleepy_lock_interval_ns_set(void *data, u64 val) argument 896 pv_sleepy_lock_interval_ns_get(void *data, u64 *val) argument 905 pv_sleepy_lock_factor_set(void *data, u64 val) argument 912 pv_sleepy_lock_factor_get(void *data, u64 *val) argument 921 pv_yield_prev_set(void *data, u64 val) argument 928 pv_yield_prev_get(void *data, u64 *val) argument 937 pv_yield_sleepy_owner_set(void *data, u64 val) argument 944 pv_yield_sleepy_owner_get(void *data, u64 *val) argument 953 pv_prod_head_set(void *data, u64 val) argument 960 pv_prod_head_get(void *data, u64 *val) argument [all...] |
/linux-master/drivers/accel/ivpu/ |
H A D | ivpu_hw_37xx.c | 111 u32 val; local 119 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0); 120 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); 121 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); 122 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val); 124 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1); 125 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); 249 u32 val = 0; local 260 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); local 277 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); local 294 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); local 304 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); local 314 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); local 324 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); local 335 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); local 346 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); local 370 u32 val; local 400 u32 val; local 432 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); local 444 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); local 462 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); local 474 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE); local 513 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); local 524 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); local 536 u32 val; local 563 u32 val; local 610 u32 val; local 735 u32 val; local 780 u32 val; local 851 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET); local [all...] |
H A D | ivpu_hw_reg_io.h | 21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__) 22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__) 27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) 28 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__) 30 #define REGV_WR32I(reg, stride, index, val) \ 31 ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #re 80 u32 val = readl(base + reg); local 90 u64 val = readq(base + reg); local 97 ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val, const char *name, const char *func) argument 105 ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val, const char *name, const char *func) argument 113 ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 stride, u32 index, u32 val, const char *name, const char *func) argument [all...] |
/linux-master/arch/mips/include/asm/ |
H A D | mipsregs.h | 1540 #define write_r10k_perf_cntr(counter,val) \ 1545 : "r" (val), "i" (counter)); \ 1559 #define write_r10k_perf_cntl(counter,val) \ 1564 : "r" (val), "i" (counter)); \ 1666 #define __write_ulong_c0_register(reg, sel, val) \ 1669 __write_32bit_c0_register(reg, sel, val); \ 1671 __write_64bit_c0_register(reg, sel, val); \ 1725 #define __write_64bit_c0_split(source, sel, val) \ 1727 unsigned long long __tmp = (val); \ 1812 #define write_c0_index(val) __write_32bit_c0_registe [all...] |
/linux-master/drivers/misc/lkdtm/ |
H A D | heap.c | 94 int *base, *val, saw; local 110 val = kmalloc(len, GFP_KERNEL); 111 if (!val) { 112 pr_info("Unable to allocate val memory.\n"); 117 *val = 0x12345678; 118 base[offset] = *val; 125 if (saw != *val) { 133 kfree(val); 138 int *base, val, saw; local 168 val 217 int saw, *val; local 254 u8 *val; local 286 u8 *val; local 318 int *val; local 335 int *val; local [all...] |
/linux-master/drivers/mfd/ |
H A D | pcf50633-gpio.c | 33 int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) argument 39 return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); 45 u8 reg, val; local 48 val = pcf50633_reg_read(pcf, reg) & 0x07; 50 return val; 56 u8 val, reg; local 59 val = !!invert << 3; 61 return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); 67 u8 reg, val; local 70 val 79 u8 reg, val, mask; local [all...] |
/linux-master/arch/arm64/include/asm/ |
H A D | percpu.h | 61 static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ 63 WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ 68 __percpu_##name##_case_##sz(void *ptr, unsigned long val) \ 76 #op_llsc "\t%" #w "[tmp], %" #w "[tmp], %" #w "[val]\n" \ 80 #op_lse "\t%" #w "[val], %[ptr]\n" \ 84 : [val] "r" ((u##sz)(val))); \ 89 __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \ 97 #op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \ 101 #op_lse "\t%" #w "[val], [all...] |
/linux-master/arch/powerpc/include/asm/ |
H A D | kvm_booke.h | 26 static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) argument 28 vcpu->arch.regs.gpr[num] = val; 36 static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) argument 38 vcpu->arch.regs.ccr = val; 46 static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val) argument 48 vcpu->arch.regs.xer = val; 62 static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val) argument 64 vcpu->arch.regs.ctr = val; 72 static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val) argument 74 vcpu->arch.regs.link = val; 82 kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val) argument 92 kvmppc_set_fpr(struct kvm_vcpu *vcpu, int i, u64 val) argument [all...] |
/linux-master/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_model.h | 12 int (*val)(struct ixgbe_fdir_filter *input, member in struct:ixgbe_mat_field 14 u32 val, u32 m); 30 u32 val, u32 m) 32 input->filter.formatted.src_ip[0] = (__force __be32)val; 39 u32 val, u32 m) 41 input->filter.formatted.dst_ip[0] = (__force __be32)val; 47 { .off = 12, .val = ixgbe_mat_prgm_sip, 49 { .off = 16, .val = ixgbe_mat_prgm_dip, 51 { .val = NULL } /* terminal node */ 56 u32 val, u3 28 ixgbe_mat_prgm_sip(struct ixgbe_fdir_filter *input, union ixgbe_atr_input *mask, u32 val, u32 m) argument 37 ixgbe_mat_prgm_dip(struct ixgbe_fdir_filter *input, union ixgbe_atr_input *mask, u32 val, u32 m) argument 54 ixgbe_mat_prgm_ports(struct ixgbe_fdir_filter *input, union ixgbe_atr_input *mask, u32 val, u32 m) argument 85 u32 val; member in struct:ixgbe_nexthdr [all...] |
/linux-master/tools/testing/selftests/bpf/prog_tests/ |
H A D | btf_map_in_map.c | 28 int err, key = 0, val, i, fd; local 53 bpf_map_lookup_elem(map1_fd, &key, &val); 54 CHECK(val != 1, "inner1", "got %d != exp %d\n", val, 1); 55 bpf_map_lookup_elem(map2_fd, &key, &val); 56 CHECK(val != 2, "inner2", "got %d != exp %d\n", val, 2); 57 bpf_map_lookup_elem(map3_fd, &key, &val); 58 CHECK(val != 3, "inner3", "got %d != exp %d\n", val, [all...] |
/linux-master/drivers/gpu/drm/sprd/ |
H A D | megacores_pll.c | 127 static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[]) argument 131 regmap_write(regmap, 0x31, val[CLK]); 132 regmap_write(regmap, 0x41, val[DATA]); 133 regmap_write(regmap, 0x51, val[DATA]); 134 regmap_write(regmap, 0x61, val[DATA]); 135 regmap_write(regmap, 0x71, val[DATA]); 137 regmap_write(regmap, 0x90, val[CLK]); 138 regmap_write(regmap, 0xa0, val[DATA]); 139 regmap_write(regmap, 0xb0, val[DATA]); 140 regmap_write(regmap, 0xc0, val[DAT 222 u8 val[2]; local [all...] |
/linux-master/drivers/net/wireless/intel/iwlwifi/ |
H A D | iwl-devtrace-io.h | 18 TP_PROTO(const struct device *dev, u32 offs, u32 val), 19 TP_ARGS(dev, offs, val), 23 __field(u32, val) 28 __entry->val = val; 31 __get_str(dev), __entry->offs, __entry->val) 35 TP_PROTO(const struct device *dev, u32 offs, u8 val), 36 TP_ARGS(dev, offs, val), 40 __field(u8, val) 45 __entry->val [all...] |
/linux-master/include/linux/ |
H A D | iopoll.h | 20 * @val: Variable to read the value into 21 * @cond: Break condition (usually involving @val) 30 * case, the last read value at @args is stored in @val. Must not 36 #define read_poll_timeout(op, val, cond, sleep_us, timeout_us, \ 46 (val) = op(args); \ 51 (val) = op(args); \ 65 * @val: Variable to read the value into 66 * @cond: Break condition (usually involving @val) 75 * case, the last read value at @args is stored in @val. 84 #define read_poll_timeout_atomic(op, val, con [all...] |
/linux-master/arch/x86/kernel/cpu/mce/ |
H A D | intel.c | 140 u64 val; local 143 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); local 144 val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK; 145 wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh); 175 static bool cmci_skip_bank(int bank, u64 *val) argument 186 rdmsrl(MSR_IA32_MCx_CTL2(bank), *val); 189 if (*val & MCI_CTL2_CMCI_EN) { 205 static u64 cmci_pick_threshold(u64 val, int *bios_zero_thresh) argument 207 if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD) 208 return val; 229 cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_wrong_thresh) argument 234 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); local 235 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); local 284 u64 val; local 322 u64 val; local 328 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); local 427 u64 val; local 440 u64 val; local [all...] |