Searched refs:bw (Results 151 - 175 of 389) sorted by relevance

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/linux-master/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmac.c119 u8 bw; local
186 switch (rate->bw) {
188 bw = IEEE80211_STA_RX_BW_160;
191 bw = IEEE80211_STA_RX_BW_80;
194 bw = IEEE80211_STA_RX_BW_40;
197 bw = IEEE80211_STA_RX_BW_20;
202 u8 offs = 24 + 2 * bw;
207 if (val & BIT(12 + bw))
615 u8 bw, mode, nss = td->tx_rate_nss; local
666 bw
[all...]
/linux-master/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c.c732 u8 primary_ch, enum rtw89_bandwidth bw)
736 if (bw == RTW89_CHANNEL_WIDTH_20) {
738 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
744 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
1071 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) argument
1076 switch (bw) {
1097 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, argument
1100 if (bw == RTW89_CHANNEL_WIDTH_20) {
1110 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, argument
1115 switch (bw) {
731 rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, u8 primary_ch, enum rtw89_bandwidth bw) argument
1221 u8 bw = chan->band_width; local
[all...]
H A Drtw8852c_rfk.c1913 dpk->bp[path][kidx].bw = chan->band_width;
1923 dpk->bp[path][kidx].bw == 0 ? "20M" :
1924 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
2096 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160)
2105 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160) {
2108 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
2111 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
2119 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160 ? "160M" :
2120 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
2121 dpk->bp[path][kidx].bw
2897 enum rtw89_bandwidth bw = chan->band_width; local
3815 _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, enum rtw89_bandwidth bw, bool is_dav) argument
3860 _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, enum rtw89_bandwidth bw) argument
3954 _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, enum rtw89_bandwidth bw) argument
4052 rtw8852c_ctrl_bw_ch(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 central_ch, enum rtw89_band band, enum rtw89_bandwidth bw) argument
[all...]
H A Drtw8852b_rfk.c1772 dpk->bp[path][kidx].bw = chan->band_width;
1782 dpk->bp[path][kidx].bw == 0 ? "20M" :
1783 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1922 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
1959 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
1961 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
1967 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
1968 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2369 if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 &&
3946 enum rtw89_bandwidth bw, boo
3945 _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, enum rtw89_bandwidth bw, bool dav) argument
3987 _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, enum rtw89_bandwidth bw) argument
4117 _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw, enum rtw89_rf_path path) argument
4138 _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, enum rtw89_bandwidth bw) argument
4153 rtw8852b_ctrl_bw_ch(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 central_ch, enum rtw89_band band, enum rtw89_bandwidth bw) argument
[all...]
H A Dcore.c636 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
1722 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; local
1743 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1748 status->bw == bw;
1787 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
2002 u8 bw; local
2033 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
2036 bw
[all...]
H A Dphy.c128 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
132 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
137 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
473 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
640 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
1108 u8 bw:4; member in struct:rtw89_phy_bb_gain_arg::__anon1544::__anon1545::__anon1546
1162 u8 bw = arg.bw; local
1169 switch (bw) {
1232 "bb rpl ofst {0x%x:0x%x} with unknown bw
1845 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, const struct rtw89_rate_desc *rate_desc) argument
1905 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) argument
2139 u8 bw = chan->band_width; local
2329 u8 bw = chan->band_width; local
2445 u8 bw = chan->band_width; local
2480 u8 bw = chan->band_width; local
2523 u8 mode, rate, bw, giltf, mac_id; local
[all...]
H A Drtw8852a.c780 u8 primary_ch, enum rtw89_bandwidth bw)
784 if (bw == RTW89_CHANNEL_WIDTH_20) {
786 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
792 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
949 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) argument
961 switch (bw) {
995 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, argument
999 switch (bw) {
1047 rtw89_warn(rtwdev, "Fail to switch bw (bw
779 rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, u8 primary_ch, enum rtw89_bandwidth bw) argument
[all...]
H A Drtw8851b_rfk.c1758 dpk->bp[path][kidx].bw = chan->channel;
1768 dpk->bp[path][kidx].bw == 0 ? "20M" :
1769 dpk->bp[path][kidx].bw == 1 ? "40M" :
1770 dpk->bp[path][kidx].bw == 2 ? "80M" : "160M");
1830 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
1833 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
1842 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
1843 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2076 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
3403 enum rtw89_bandwidth bw, boo
3402 _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, enum rtw89_bandwidth bw, bool dav) argument
3444 _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, enum rtw89_bandwidth bw) argument
3570 _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw, enum rtw89_rf_path path) argument
3591 _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, enum rtw89_bandwidth bw) argument
3606 rtw8851b_ctrl_bw_ch(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 central_ch, enum rtw89_band band, enum rtw89_bandwidth bw) argument
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_mac.c183 u8 phy, rate_idx, nss, bw = 0; local
191 bw = 2;
193 bw = 1;
201 bw = 1;
220 rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
717 status->bw = RATE_INFO_BW_40;
720 status->bw = RATE_INFO_BW_80;
/linux-master/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c.c2190 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) argument
2219 switch (bw) {
2267 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, argument
2277 switch (bw) {
2372 switch (bw) {
2425 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, argument
2428 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
2429 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
2430 rtw8822c_set_channel_rf(rtwdev, channel, bw);
2591 pkt_stat->bw
2601 u8 rxsc, bw; local
3412 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; local
4395 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) argument
4437 u8 nrx, bw; local
[all...]
H A Dtx.c70 le32_encode_bits(pkt_info->bw, RTW_TX_DESC_W5_DATA_BW) |
342 u8 bw = RTW_CHANNEL_WIDTH_20; local
372 bw = si->bw_mode;
384 pkt_info->bw = bw;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c225 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
227 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;
720 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;
1721 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1725 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1727 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1732 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1737 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1740 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1744 context->bw_ctx.bw
[all...]
/linux-master/drivers/net/wireless/broadcom/b43/
H A Dxmit.c172 u16 bw; local
175 bw = B43_TXH_PHY1_BW_20;
177 bw = B43_TXH_PHY1_BW_20;
181 control = bw;
183 control = bw;
/linux-master/drivers/staging/rtl8723bs/hal/
H A Drtl8723b_cmd.c330 void rtl8723b_set_FwMacIdConfig_cmd(struct adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask) argument
337 SET_8723B_H2CCMD_MACID_CFG_BW(u1H2CMacIdConfigParm, bw);
743 u8 bw; local
750 bw = psta->bw_mode;
755 rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, raid, bw, shortGI, mask);
/linux-master/drivers/media/dvb-frontends/
H A Ddib8000.c617 static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw) argument
622 if (bw == 0)
623 bw = 6000;
672 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw) argument
674 dprintk("ifreq: %d %x, inversion: %d\n", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
677 (u16) (((bw->internal * 1000) >> 16) & 0xffff));
679 (u16) ((bw->internal * 1000) & 0xffff));
681 dib8000_write_word(state, 23, (u16) (((bw
745 dib8000_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio) argument
[all...]
H A Dzl10353.c117 u8 bw = bandwidth / 1000000; local
123 value = (bw * value) + adc_clock / 2;
126 dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
127 __func__, bw, adc_clock, *nominal_rate);
H A Dstb6100.c245 u32 bw; local
253 bw = (f + 5) * 2000; /* x2 for ZIF */
255 *bandwidth = state->bandwidth = bw * 1000;
272 else if (bandwidth <= 5000000) /* bw/2 min = 5Mhz for F=0 */
274 else /* if 5 < bw/2 < 36 */
/linux-master/kernel/locking/
H A Drtmutex.c453 struct rt_mutex_waiter *bw = __node_2_waiter(b); local
455 if (rt_waiter_node_less(&aw->tree, &bw->tree))
461 if (rt_waiter_node_less(&bw->tree, &aw->tree))
466 if (!bw->ww_ctx)
470 bw->ww_ctx->stamp) < 0;
/linux-master/drivers/cxl/core/
H A Dpci.c1039 long bw; local
1041 bw = pcie_link_speed_mbps(pdev);
1042 if (bw < 0)
1044 bw /= BITS_PER_BYTE;
1046 return cxl_flit_size(pdev) * MEGA / bw;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c112 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) {
116 return dcn32_helper_mall_bytes_to_ways(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
545 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
788 if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_KHZ)
789 context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ;
/linux-master/drivers/net/wireless/virtual/
H A Dmac80211_hwsim.c700 enum nl80211_chan_width bw; member in struct:mac80211_hwsim_data
966 static int hwsim_get_chanwidth(enum nl80211_chan_width bw) argument
968 switch (bw) {
1765 rx_status.bw = RATE_INFO_BW_40;
1767 rx_status.bw = RATE_INFO_BW_80;
1769 rx_status.bw = RATE_INFO_BW_160;
1771 rx_status.bw = RATE_INFO_BW_20;
1942 confbw = data->bw;
2025 /* initialize to data->bw for 5/10 MHz handling */
2026 enum nl80211_chan_width bw local
2581 u32 bw = U32_MAX; local
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dphy.c476 int bw; local
482 bw = BW_20;
485 bw = BW_40;
488 bw = BW_80;
491 bw = BW_10;
500 mt76x02_mcu_function_select(dev, BW_SETTING, bw);
/linux-master/drivers/media/usb/dvb-usb/
H A Daf9005-fe.c530 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw) argument
541 switch (bw) {
569 err("Invalid bandwidth %d.", bw);
764 static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw) argument
767 switch (bw) {
778 err("Invalid bandwidth %d.", bw);
1098 deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
/linux-master/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dmcu.c721 u8 bw; member in struct:__anon1275::roc_acquire_tlv
741 .bw = CMD_CBW_20MHZ,
808 u8 bw; member in struct:__anon1279
825 .bw = mt76_connac_chan_bw(chandef),
1129 u8 bw; member in struct:__anon1288::config_tlv
1152 req.tlv.bw = ch_width[chandef->width];
/linux-master/include/linux/mtd/
H A Dmap.h379 int bw = 8 * map_bankwidth(map); local
381 r.x[0] = (1UL << bw) - 1;

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