realtek/rtw89/phy.c

129 		mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
133 		mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
146 		mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
478 		    "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
645 		    "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
1113 				u8 bw:4;
1167 	u8 bw = arg.bw;
1174 	switch (bw) {
1237 			   "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
1238 			   arg.addr, data, bw);
1850 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
1859 	byr_head = &rtwdev->byr[band][bw];
1911 			      u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
1927 		lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
1931 		lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
1934 		lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
1938 		lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
1941 		lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
1945 		lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
1961 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch)		\
1967 							      bw, ntx,	\
2144 	u8 bw = chan->band_width;
2148 	switch (bw) {
2334 	u8 bw = chan->band_width;
2338 	switch (bw) {
2450 	u8 bw = chan->band_width;
2456 		    "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
2485 	u8 bw = chan->band_width;
2491 		    "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
2528 	u8 mode, rate, bw, giltf, mac_id;
2539 	bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
2547 		bw |= u8_encode_bits(t, BIT(2));
2618 	ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
2666 			    "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
2667 			    dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
2731 			    "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
2732 			    rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,