/linux-master/arch/x86/kernel/ |
H A D | umip.c | 338 int nr_copied, reg_offset, dummy_data_size, umip_inst; local 380 reg_offset = insn_get_modrm_rm_off(&insn, regs); 387 if (reg_offset < 0) 390 reg_addr = (unsigned long *)((unsigned long)regs + reg_offset);
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/linux-master/sound/soc/sof/amd/ |
H A D | acp-trace.c | 60 dtrace_params->buffer.phy_addr = stream->reg_offset;
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/linux-master/arch/arm64/kvm/vgic/ |
H A D | vgic-mmio.h | 9 unsigned int reg_offset; member in struct:vgic_register_region 69 .reg_offset = off, \ 81 .reg_offset = off, \ 91 .reg_offset = off, \
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/linux-master/drivers/leds/blink/ |
H A D | leds-bcm63138.c | 92 int reg_offset = (led->pin >> fls((BCM63138_LEDS_PER_REG - 1))) * 4; local 95 bcm63138_leds_update_bits(leds, BCM63138_FLASH_RATE_CTRL1 + reg_offset, 103 int reg_offset = (led->pin >> fls((BCM63138_LEDS_PER_REG - 1))) * 4; local 106 bcm63138_leds_update_bits(leds, BCM63138_BRIGHT_CTRL1 + reg_offset,
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/linux-master/drivers/irqchip/ |
H A D | irq-bcm2836.c | 25 static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset, argument 29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; 34 static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset, argument 38 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
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H A D | irq-meson-gpio.c | 207 unsigned int reg_offset; local 210 reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; 213 meson_gpio_irq_update_bits(ctl, reg_offset, 222 unsigned int reg_offset; local 226 reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2); 228 meson_gpio_irq_update_bits(ctl, reg_offset,
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/linux-master/include/linux/platform_data/ |
H A D | mmc-omap.h | 36 u16 reg_offset; member in struct:omap_mmc_platform_data
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/linux-master/drivers/media/platform/ti/omap3isp/ |
H A D | isp.h | 281 * @reg_offset: Register offset to read from. 287 u32 reg_offset) 289 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); 297 * @reg_offset: Register offset to write into. 301 enum isp_mem_resources isp_mmio_range, u32 reg_offset) 303 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset); 286 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, u32 reg_offset) argument 300 isp_reg_writel(struct isp_device *isp, u32 reg_value, enum isp_mem_resources isp_mmio_range, u32 reg_offset) argument
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/linux-master/drivers/watchdog/ |
H A D | marvell_gti_wdt.c | 38 #define GTI_CWD_WDOG(reg_offset) (0x8 * (reg_offset)) 59 #define GTI_CWD_POKE(reg_offset) (0x10000 + 0x8 * (reg_offset))
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/linux-master/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_mbx.c | 274 u32 reg_offset = (vf_number < 32) ? 0 : 1; local 280 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); 286 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); 293 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), BIT(vf_shift));
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_umsch_mm.h | 184 uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \ 186 *adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2); \ 189 WREG32(reg_offset, value); \
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H A D | jpeg_v2_0.c | 591 uint32_t reg_offset = (reg << 2); local 603 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 606 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 608 amdgpu_ring_write(ring, reg_offset); 632 uint32_t reg_offset = (reg << 2); local 636 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 639 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 641 amdgpu_ring_write(ring, reg_offset); [all...] |
H A D | gfx_v8_0.c | 2078 u32 reg_offset; local 2083 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2084 modearray[reg_offset] = 0; 2086 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2087 mod2array[reg_offset] = 0; 2251 for (reg_offset [all...] |
H A D | nv.c | 359 u32 sh_num, u32 reg_offset) 367 val = RREG32(reg_offset); 377 u32 sh_num, u32 reg_offset) 380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 382 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 384 return RREG32(reg_offset); 389 u32 sh_num, u32 reg_offset, u32 *value) 397 if (!adev->reg_offset[en->hwip][en->inst]) 399 else if (reg_offset != (adev->reg_offset[e 358 nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) argument 375 nv_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) argument 388 nv_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) argument [all...] |
H A D | soc21.c | 279 u32 sh_num, u32 reg_offset) 287 val = RREG32(reg_offset); 297 u32 sh_num, u32 reg_offset) 300 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 302 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 304 return RREG32(reg_offset); 309 u32 sh_num, u32 reg_offset, u32 *value) 317 if (!adev->reg_offset[en->hwip][en->inst]) 319 else if (reg_offset != (adev->reg_offset[e 278 soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) argument 295 soc21_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) argument 308 soc21_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) argument [all...] |
H A D | hdp_v5_0.c | 35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 37 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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H A D | hdp_v5_2.c | 35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 39 (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
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H A D | hdp_v4_0.c | 44 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 46 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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/linux-master/sound/soc/amd/acp/ |
H A D | acp-legacy-common.c | 57 physical_addr = stream->reg_offset + MEM_WINDOW_START; 121 phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset; 129 phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset; 140 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; 148 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; 159 phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset; 167 phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
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H A D | acp-pdm.c | 48 physical_addr = stream->reg_offset + MEM_WINDOW_START; 149 stream->reg_offset = ACP_REGION2_OFFSET;
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/linux-master/drivers/pinctrl/realtek/ |
H A D | pinctrl-rtd.c | 307 reg_off = config_desc->reg_offset; 320 reg_off = config_desc->reg_offset; 332 reg_off = config_desc->reg_offset; 345 reg_off = config_desc->reg_offset; 358 reg_off = config_desc->reg_offset; 366 reg_off = config_desc->reg_offset; 400 reg_off = config_desc->reg_offset; 418 reg_off = sconfig_desc->reg_offset; 435 reg_off = sconfig_desc->reg_offset; 452 reg_off = config_desc->reg_offset; [all...] |
/linux-master/drivers/clk/microchip/ |
H A D | clk-mpfs.c | 54 u32 reg_offset; member in struct:mpfs_msspll_hw_clock 67 u32 reg_offset; member in struct:mpfs_msspll_out_hw_clock 76 u32 reg_offset; member in struct:mpfs_cfg_hw_clock 122 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 143 .reg_offset = _offset, \ 182 .reg_offset = _offset, \ 209 msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset; 230 .reg_offset = _offset, \ 253 .reg_offset = REG_RTC_CLOCK_CR, 269 cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; [all...] |
/linux-master/sound/soc/fsl/ |
H A D | fsl_sai.c | 89 unsigned int ofs = sai->soc_data->reg_offset; 191 unsigned int ofs = sai->soc_data->reg_offset; 276 unsigned int ofs = sai->soc_data->reg_offset; 406 unsigned int reg, ofs = sai->soc_data->reg_offset; 517 unsigned int ofs = sai->soc_data->reg_offset; 715 unsigned int ofs = sai->soc_data->reg_offset; 734 unsigned int ofs = sai->soc_data->reg_offset; 774 unsigned int ofs = sai->soc_data->reg_offset; 883 unsigned int ofs = sai->soc_data->reg_offset; 1013 unsigned int ofs = sai->soc_data->reg_offset; [all...] |
/linux-master/drivers/pinctrl/freescale/ |
H A D | pinctrl-imx1-core.c | 89 u32 value, u32 reg_offset) 91 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 116 u32 value, u32 reg_offset) 118 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 136 u32 reg_offset) 138 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 149 u32 reg_offset) 151 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 88 imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, u32 value, u32 reg_offset) argument 115 imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, u32 value, u32 reg_offset) argument 135 imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, u32 reg_offset) argument 148 imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, u32 reg_offset) argument
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/linux-master/drivers/net/wireless/ath/ath10k/ |
H A D | qmi.h | 68 __le16 reg_offset; member in struct:ath10k_shadow_reg_cfg
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