1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#include "amdgpu.h" 24#include "amdgpu_atombios.h" 25#include "hdp_v4_0.h" 26#include "amdgpu_ras.h" 27 28#include "hdp/hdp_4_0_offset.h" 29#include "hdp/hdp_4_0_sh_mask.h" 30#include <uapi/linux/kfd_ioctl.h> 31 32/* for Vega20 register name change */ 33#define mmHDP_MEM_POWER_CTRL 0x00d4 34#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 35#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 36#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 37#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 38#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 39 40static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev, 41 struct amdgpu_ring *ring) 42{ 43 if (!ring || !ring->funcs->emit_wreg) 44 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 45 else 46 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 47} 48 49static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, 50 struct amdgpu_ring *ring) 51{ 52 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) || 53 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) 54 return; 55 56 if (!ring || !ring->funcs->emit_wreg) 57 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 58 else 59 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 60 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 61} 62 63static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev, 64 void *ras_error_status) 65{ 66 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 67 68 err_data->ue_count = 0; 69 err_data->ce_count = 0; 70 71 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) 72 return; 73 74 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */ 75 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); 76}; 77 78static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 79{ 80 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) 81 return; 82 83 if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0)) 84 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); 85 else 86 /*read back hdp ras counter to reset it to 0 */ 87 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); 88} 89 90static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev, 91 bool enable) 92{ 93 uint32_t def, data; 94 95 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) || 96 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) || 97 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) || 98 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) { 99 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 100 101 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 102 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 103 else 104 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 105 106 if (def != data) 107 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 108 } else { 109 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 110 111 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 112 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 113 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 114 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 115 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 116 else 117 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 118 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 119 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 120 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 121 122 if (def != data) 123 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 124 } 125} 126 127static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, 128 u64 *flags) 129{ 130 int data; 131 132 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) { 133 /* Default enabled */ 134 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 135 return; 136 } 137 /* AMD_CG_SUPPORT_HDP_LS */ 138 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 139 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 140 *flags |= AMD_CG_SUPPORT_HDP_LS; 141} 142 143static void hdp_v4_0_init_registers(struct amdgpu_device *adev) 144{ 145 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 146 case IP_VERSION(4, 2, 1): 147 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); 148 break; 149 default: 150 break; 151 } 152 153 /* Do not program registers if VF */ 154 if (amdgpu_sriov_vf(adev)) 155 return; 156 157 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 158 159 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0)) 160 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); 161 162 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 163 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 164} 165 166struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = { 167 .query_ras_error_count = hdp_v4_0_query_ras_error_count, 168 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count, 169}; 170 171struct amdgpu_hdp_ras hdp_v4_0_ras = { 172 .ras_block = { 173 .hw_ops = &hdp_v4_0_ras_hw_ops, 174 }, 175}; 176 177const struct amdgpu_hdp_funcs hdp_v4_0_funcs = { 178 .flush_hdp = hdp_v4_0_flush_hdp, 179 .invalidate_hdp = hdp_v4_0_invalidate_hdp, 180 .update_clock_gating = hdp_v4_0_update_clock_gating, 181 .get_clock_gating_state = hdp_v4_0_get_clockgating_state, 182 .init_registers = hdp_v4_0_init_registers, 183}; 184