/linux-master/arch/arm/mach-shmobile/ |
H A D | setup-r8a7778.c | 27 void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); local 29 BUG_ON(!base); 34 writel(0x73ffffff, base + INT2NTSR0); 35 writel(0xffffffff, base + INT2NTSR1); 38 writel(0x08330773, base + INT2SMSKCR0); 39 writel(0x00311110, base + INT2SMSKCR1); 41 iounmap(base);
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/linux-master/arch/mips/sgi-ip32/ |
H A D | ip32-memory.c | 24 u64 base, size; local 31 base = (bankctl & CRIME_MEM_BANK_CONTROL_ADDR) << 25; 32 if (bank != 0 && base == 0) 36 if (base + size > (256 << 20)) 37 base += CRIME_HI_MEM_BASE; 39 printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n", 40 bank, base, size >> 20); 41 memblock_add(base, size);
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/linux-master/drivers/clk/imx/ |
H A D | clk-imx6sl.c | 185 void __iomem *base; local 203 base = of_iomap(np, 0); 204 WARN_ON(!base); 206 anatop_base = base; 208 hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 209 hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 210 hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 211 hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 212 hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 213 hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base [all...] |
H A D | clk-imx6q.c | 439 void __iomem *anatop_base, *base; local 461 anatop_base = base = of_iomap(np, 0); 462 WARN_ON(!base); 473 hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 474 hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 475 hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 476 hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 477 hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 478 hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 479 hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base [all...] |
/linux-master/drivers/fpga/ |
H A D | dfl-fme-error.c | 46 void __iomem *base; local 49 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); 52 value = readq(base + PCIE0_ERROR); 63 void __iomem *base; local 70 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); 73 writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK); 75 v = readq(base + PCIE0_ERROR); 77 writeq(v, base + PCIE0_ERROR); 81 writeq(0ULL, base + PCIE0_ERROR_MASK); 91 void __iomem *base; local 108 void __iomem *base; local 135 void __iomem *base; local 147 void __iomem *base; local 160 void __iomem *base; local 178 void __iomem *base; local 205 void __iomem *base; local 222 void __iomem *base; local 252 void __iomem *base; local 269 void __iomem *base; local 318 void __iomem *base; local [all...] |
/linux-master/drivers/remoteproc/ |
H A D | qcom_pil_info.c | 16 * region followed by a 64 bit base address and 32 bit size, both little 23 void __iomem *base; member in struct:pil_reloc 34 void __iomem *base; local 38 if (_reloc.base) 50 base = ioremap(imem.start, resource_size(&imem)); 51 if (!base) { 56 memset_io(base, 0, resource_size(&imem)); 58 _reloc.base = base; 67 * @base 72 qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
H A D | busnv50.c | 24 #define nv50_i2c_bus(p) container_of((p), struct nv50_i2c_bus, base) 30 struct nvkm_i2c_bus base; member in struct:nv50_i2c_bus 36 nv50_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) argument 38 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); 39 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; 46 nv50_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) argument 48 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); 49 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; 56 nv50_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) argument 58 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); 64 nv50_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) argument 72 nv50_i2c_bus_init(struct nvkm_i2c_bus *base) argument [all...] |
/linux-master/include/sound/ |
H A D | snd_wavefront.h | 23 unsigned long base; /* I/O port address */ member in struct:_snd_wavefront_midi 52 unsigned long base; /* low i/o port address */ member in struct:_snd_wavefront 55 #define mpu_data_port base 56 #define mpu_command_port base + 1 /* write semantics */ 57 #define mpu_status_port base + 1 /* read semantics */ 58 #define data_port base + 2 59 #define status_port base + 3 /* read semantics */ 60 #define control_port base + 3 /* write semantics */ 61 #define block_port base + 4 /* 16 bit, writeonly */ 62 #define last_block_port base [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | gf100.c | 32 gf100_fb_intr(struct nvkm_fb *base) argument 34 struct gf100_fb *fb = gf100_fb(base); 35 struct nvkm_subdev *subdev = &fb->base.subdev; 45 gf100_fb_oneinit(struct nvkm_fb *base) argument 47 struct gf100_fb *fb = gf100_fb(base); 48 struct nvkm_device *device = fb->base.subdev.device; 49 int ret, size = 1 << (fb->base.page ? fb->base.page : 17); 55 true, &fb->base.mmu_rd); 60 true, &fb->base 87 gf100_fb_init(struct nvkm_fb *base) argument 99 gf100_fb_dtor(struct nvkm_fb *base) argument [all...] |
H A D | ramseq.h | 6 #define ram_init(s,p) hwsq_init(&(s)->base, (p)) 7 #define ram_exec(s,e) hwsq_exec(&(s)->base, (e)) 9 #define ram_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) 10 #define ram_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) 11 #define ram_nuke(s,r) hwsq_nuke(&(s)->base, &(s)->r_##r) 12 #define ram_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) 13 #define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) 14 #define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) 15 #define ram_wait_vblank(s) hwsq_wait_vblank(&(s)->base) 16 #define ram_nsec(s,n) hwsq_nsec(&(s)->base, ( [all...] |
/linux-master/drivers/char/hw_random/ |
H A D | histb-rng.c | 26 void __iomem *base; member in struct:histb_rng_priv 34 static int histb_rng_wait(void __iomem *base) argument 38 return readl_relaxed_poll_timeout(base + RNG_STAT, val, 42 static void histb_rng_init(void __iomem *base, unsigned int depth) argument 46 val = readl_relaxed(base + RNG_CTRL); 57 writel_relaxed(val, base + RNG_CTRL); 63 void __iomem *base = priv->base; local 66 if (!(readl_relaxed(base + RNG_STAT) & DATA_COUNT)) { 69 if (histb_rng_wait(base)) { 81 histb_rng_get_depth(void __iomem *base) argument 90 void __iomem *base = priv->base; local 100 void __iomem *base = priv->base; local 123 void __iomem *base; local [all...] |
/linux-master/drivers/net/ethernet/marvell/mvpp2/ |
H A D | mvpp2_tai.c | 59 void __iomem *base; member in struct:mvpp2_tai 90 static void mvpp22_tai_read_ts(struct timespec64 *ts, void __iomem *base) argument 92 ts->tv_sec = (u64)mvpp2_tai_read(base + 0) << 32 | 93 mvpp2_tai_read(base + 4) << 16 | 94 mvpp2_tai_read(base + 8); 96 ts->tv_nsec = mvpp2_tai_read(base + 12) << 16 | 97 mvpp2_tai_read(base + 16); 100 readl_relaxed(base + 20); 101 readl_relaxed(base + 24); 105 void __iomem *base) 104 mvpp2_tai_write_tlv(const struct timespec64 *ts, u32 frac, void __iomem *base) argument 116 mvpp2_tai_op(u32 op, void __iomem *base) argument 168 void __iomem *base; local 210 void __iomem *base; local 241 void __iomem *base; local 281 void __iomem *base; local 313 void __iomem *base = tai->base; local 332 void __iomem *base = tai->base; local [all...] |
/linux-master/drivers/atm/ |
H A D | nicstarmac.c | 106 writel((val),(base)+(reg)) 108 readl((base)+(reg)) 117 u_int32_t nicstar_read_eprom_status(virt_addr_t base) 124 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; 127 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 137 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 139 rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) 141 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 145 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2); 157 static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_ argument 202 nicstar_init_eprom(virt_addr_t base) argument 234 nicstar_read_eprom(virt_addr_t base, u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/volt/ |
H A D | gk20a.c | 22 #define gk20a_volt(p) container_of((p), struct gk20a_volt, base) 93 gk20a_volt_vid_get(struct nvkm_volt *base) argument 95 struct gk20a_volt *volt = gk20a_volt(base); 100 for (i = 0; i < volt->base.vid_nr; i++) 101 if (volt->base.vid[i].uv >= uv) 108 gk20a_volt_vid_set(struct nvkm_volt *base, u8 vid) argument 110 struct gk20a_volt *volt = gk20a_volt(base); 111 struct nvkm_subdev *subdev = &volt->base.subdev; 113 nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv); 114 return regulator_set_voltage(volt->vdd, volt->base 118 gk20a_volt_set_id(struct nvkm_volt *base, u8 id, int condition) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
H A D | usernv04.c | 24 #define nv04_dmaobj(p) container_of((p), struct nv04_dmaobj, base) 34 struct nvkm_dmaobj base; member in struct:nv04_dmaobj 41 nv04_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, argument 44 struct nv04_dmaobj *dmaobj = nv04_dmaobj(base); 45 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; 46 u64 offset = dmaobj->base.start & 0xfffff000; 47 u64 adjust = dmaobj->base.start & 0x00000fff; 48 u32 length = dmaobj->base.limit - dmaobj->base.start; 54 if (!dmaobj->base [all...] |
/linux-master/drivers/rtc/ |
H A D | rtc-ssd202d.c | 48 void __iomem *base; member in struct:ssd202d_rtc 51 static u8 read_iso_en(void __iomem *base) argument 53 return readb(base + REG_RTC_TEST) & 0x1; 56 static u8 read_iso_ctrl_ack(void __iomem *base) argument 58 return (readb(base + REG_ISOACK) & ISO_CTRL_ACK_MASK) >> ISO_CTRL_ACK_SHIFT; 73 writeb(sequence[i] & ISO_CTRL_MASK, priv->base + REG_ISO_CTRL); 76 20 * 100, true, priv->base); 87 ret = read_poll_timeout(read_iso_en, val, val, 100, 22 * 100, true, priv->base); 95 unsigned int field, unsigned int *base) 103 val = readw(priv->base 94 ssd202d_rtc_read_reg(struct ssd202d_rtc *priv, unsigned int reg, unsigned int field, unsigned int *base) argument 114 ssd202d_rtc_write_reg(struct ssd202d_rtc *priv, unsigned int reg, unsigned int field, u32 base) argument 153 unsigned int sw0, base, counter; local [all...] |
/linux-master/drivers/gpu/drm/omapdrm/dss/ |
H A D | hdmi4_cec.c | 58 u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; 71 msg.msg[0] = hdmi_read_reg(core->base, 73 msg.msg[1] = hdmi_read_reg(core->base, 79 hdmi_read_reg(core->base, reg); 85 hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1); 87 while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1) 93 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; 99 u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0); 100 u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1); 102 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_ [all...] |
/linux-master/include/crypto/internal/ |
H A D | kpp.h | 24 char head[offsetof(struct kpp_alg, base)]; 25 struct crypto_instance base; member in struct:kpp_instance::__anon3263::__anon3264 33 * @base: Internal. Generic crypto core spawn state. 42 struct crypto_spawn base; member in struct:crypto_kpp_spawn 78 return crypto_tfm_ctx(&tfm->base); 83 return crypto_tfm_ctx_dma(&tfm->base); 88 crypto_request_complete(&req->base, err); 108 return &inst->s.base; 119 return container_of(inst, struct kpp_instance, s.base); 130 return kpp_instance(crypto_tfm_alg_instance(&kpp->base)); [all...] |
H A D | akcipher.h | 17 char head[offsetof(struct akcipher_alg, base)]; 18 struct crypto_instance base; member in struct:akcipher_instance::__anon3257::__anon3258 25 struct crypto_spawn base; member in struct:crypto_akcipher_spawn 61 return crypto_tfm_ctx(&tfm->base); 66 return crypto_tfm_ctx_dma(&tfm->base); 72 crypto_request_complete(&req->base, err); 83 return container_of(&inst->alg.base, struct crypto_instance, alg); 89 return container_of(&inst->alg, struct akcipher_instance, alg.base); 95 return akcipher_instance(crypto_tfm_alg_instance(&akcipher->base)); 110 return crypto_spawn_tfm2(&spawn->base); [all...] |
/linux-master/arch/x86/platform/intel-quark/ |
H A D | imr_selftest.c | 61 phys_addr_t base = virt_to_phys(&_text); local 62 size_t size = virt_to_phys(&__end_rodata) - base; 71 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU); 72 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); 74 /* Test overlap with base inside of existing. */ 75 base += size - IMR_ALIGN; 76 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU); 77 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base [all...] |
/linux-master/drivers/clocksource/ |
H A D | timer-goldfish.c | 16 void __iomem *base; member in struct:goldfish_timer 32 void __iomem *base = timerdrv->base; local 40 time_low = gf_ioread32(base + TIMER_TIME_LOW); 41 time_high = gf_ioread32(base + TIMER_TIME_HIGH); 51 void __iomem *base = timerdrv->base; local 53 gf_iowrite32(0, base + TIMER_ALARM_HIGH); 54 gf_iowrite32(0, base + TIMER_ALARM_LOW); 55 gf_iowrite32(1, base 63 void __iomem *base = timerdrv->base; local 74 void __iomem *base = timerdrv->base; local 91 void __iomem *base = timerdrv->base; local 100 goldfish_timer_init(int irq, void __iomem *base) argument [all...] |
/linux-master/drivers/gpu/drm/ |
H A D | drm_displayid.c | 13 const struct displayid_header *base; local 15 if (sizeof(*base) > length - index) 18 base = (const struct displayid_header *)&displayid[index]; 20 return base; 28 const struct displayid_header *base; local 30 base = displayid_get_header(displayid, length, idx); 31 if (IS_ERR(base)) 32 return base; 34 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 35 base 57 const struct displayid_header *base; local 140 const struct displayid_header *base; local [all...] |
/linux-master/drivers/crypto/starfive/ |
H A D | jh7110-hash.c | 44 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, 53 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, 65 writel(ctx->keylen, cryp->base + STARFIVE_HASH_SHAWKLEN); 70 writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); 73 writel(*key, cryp->base + STARFIVE_HASH_SHAWKR); 78 writeb(*cl, cryp->base + STARFIVE_HASH_SHAWKR); 101 writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); 103 csr.v = readl(cryp->base + STARFIVE_HASH_SHACSR); 107 stat = readl(cryp->base + STARFIVE_IE_MASK_OFFSET); 109 writel(stat, cryp->base [all...] |
/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_dp_tunnel.c | 73 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 87 encoder->base.base.id, encoder->base.name, 109 encoder->base.base.id, encoder->base.name, 125 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 132 to_intel_crtc_state(crtc->base.state); 140 encoder->base [all...] |
/linux-master/drivers/gpu/drm/vmwgfx/ |
H A D | vmwgfx_simple_resource.c | 34 * @base: The TTM base object implementing user-space visibility. 38 struct ttm_base_object base; member in struct:vmw_user_simple_resource 100 ttm_base_object_kfree(usimple, base); 114 struct ttm_base_object *base = *p_base; local 116 container_of(base, struct vmw_user_simple_resource, base); 161 usimple->base.shareable = false; 162 usimple->base.tfile = NULL; 173 ret = ttm_base_object_init(tfile, &usimple->base, fals 207 struct ttm_base_object *base; local [all...] |