omapdrm/dss/hdmi4_cec.c

58 	u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
71 			msg.msg[0] = hdmi_read_reg(core->base,
73 			msg.msg[1] = hdmi_read_reg(core->base,
79 					hdmi_read_reg(core->base, reg);
85 		hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
87 		while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
93 		cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
99 	u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
100 	u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
102 	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
103 	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
108 		REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
110 		u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
116 		REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
128 	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
130 		temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
144 	hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
147 		temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
161 		hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
162 		hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
163 		REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
166 		REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
178 	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
195 	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
196 		hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
197 	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
198 		hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
203 	REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
209 	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22);
214 	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02);
217 	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
219 	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);
221 	temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
224 		hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);
231 		temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
233 		hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
238 	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
250 		hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
251 		hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
255 		v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
257 		hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
259 		v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
261 		hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
281 	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
284 	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
288 	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);
291 	hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));
297 	hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
302 	hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);
305 		hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
309 	hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
340 	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);