Searched refs:reset (Results 201 - 225 of 530) sorted by relevance

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/u-boot/arch/arm/mach-nexell/
H A Dtieoff.c10 #include <asm/arch/reset.h>
/u-boot/drivers/net/
H A Ddwmac_socfpga.c16 #include <reset.h>
119 dev_err(dev, "Failed to get reset: %d\n", ret);
H A Daspeed_mdio.c15 #include <reset.h>
H A Dpic32_mdio.c88 /* Clear reset bit */
116 bus->reset = pic32_mdio_reset;
/u-boot/drivers/phy/qcom/
H A Dphy-qcom-ipq4019-usb.c15 #include <reset.h>
/u-boot/drivers/usb/host/
H A Dohci-da8xx.c15 #include <reset.h>
77 /* turn off the usb clock and assert the module reset */
H A Dohci-generic.c14 #include <reset.h>
20 struct reset_ctl_bulk resets; /* reset list */
/u-boot/drivers/timer/
H A Ddw-apb-timer.c13 #include <reset.h>
68 dev_warn(dev, "Can't get reset: %d\n", ret);
/u-boot/drivers/ram/starfive/
H A Dstarfive_ddr.c18 #include <reset.h>
/u-boot/drivers/rtc/
H A Dsandbox_rtc.c97 .reset = sandbox_rtc_reset,
H A Dzynqmp_rtc.c143 .reset = zynqmp_rtc_reset,
/u-boot/drivers/reset/
H A Dstm32-reset.c14 #include <reset-uclass.h>
23 /* reset clear offset for STM32MP RCC */
36 dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
41 /* reset assert is done in rcc set register */
57 dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
62 /* reset deassert is done in rcc clr register */
/u-boot/drivers/video/
H A Draydium-rm68200.c77 struct gpio_desc reset; member in struct:rm68200_panel_priv
278 ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
281 dev_err(dev, "Warning: cannot get reset GPIO\n");
308 /* reset panel */
309 dm_gpio_set_value(&priv->reset, true);
311 dm_gpio_set_value(&priv->reset, false);
H A Dorisetech_otm8009a.c64 struct gpio_desc reset; member in struct:otm8009a_panel_priv
312 ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
315 dev_err(dev, "warning: cannot get reset GPIO\n");
336 /* reset panel */
337 dm_gpio_set_value(&priv->reset, true);
339 dm_gpio_set_value(&priv->reset, false);
/u-boot/drivers/ata/
H A Dmtk_ahci.c20 #include <reset.h>
93 dev_err(dev, "Failed to get reset: %d\n", ret);
/u-boot/drivers/clk/sunxi/
H A Dclk_a10.c13 #include <dt-bindings/reset/sun4i-a10-ccu.h>
/u-boot/cmd/
H A Dwdt.c165 "wdt reset - reset watchdog timer\n"
173 U_BOOT_SUBCMD_MKENT(reset, 1, 1, do_wdt_reset),
/u-boot/drivers/watchdog/
H A Dast_wdt.c102 .reset = ast_wdt_reset,
H A Dmpc8xxx_wdt.c95 .reset = mpc8xxx_wdt_reset,
H A Dmcf_wdt.c117 .reset = mcf_wdt_reset,
H A Dcortina_wdt.c96 /* Set 1ms timeout to reset system */
123 .reset = cortina_wdt_reset,
H A Dmtk_wdt.c116 /* Enable watchdog reset signal */
140 .reset = mtk_wdt_reset,
H A Dxilinx_tb_wdt.c111 .reset = xlnx_wdt_reset,
H A Dstm32mp_wdt.c126 .reset = stm32mp_wdt_reset,
/u-boot/test/fs/
H A Dfat-noncontig-test.sh45 # => reset
139 reset

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