1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019 STMicroelectronics - All Rights Reserved 4 * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics. 5 * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics. 6 * 7 * This rm68200 panel driver is inspired from the Linux Kernel driver 8 * drivers/gpu/drm/panel/panel-raydium-rm68200.c. 9 */ 10#include <backlight.h> 11#include <dm.h> 12#include <mipi_dsi.h> 13#include <panel.h> 14#include <asm/gpio.h> 15#include <dm/device_compat.h> 16#include <linux/delay.h> 17#include <power/regulator.h> 18 19/*** Manufacturer Command Set ***/ 20#define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */ 21#define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */ 22#define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */ 23#define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */ 24#define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */ 25#define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */ 26 27/* CMD2 P0 commands (Display Options and Power) */ 28#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */ 29#define MCS_SGOPCTR 0x16 /* Source Bias Current */ 30#define MCS_SDCTR 0x1A /* Source Output Delay Time */ 31#define MCS_INVCTR 0x1B /* Inversion Type */ 32#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */ 33#define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */ 34#define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */ 35#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */ 36#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */ 37#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */ 38#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */ 39#define MCS_SETVGN 0x52 /* VG M/S N Control */ 40#define MCS_SETVGP 0x54 /* VG M/S P Control */ 41#define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */ 42 43/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */ 44#define GOA_VSTV1 0x00 45#define GOA_VSTV2 0x07 46#define GOA_VCLK1 0x0E 47#define GOA_VCLK2 0x17 48#define GOA_VCLK_OPT1 0x20 49#define GOA_BICLK1 0x2A 50#define GOA_BICLK2 0x37 51#define GOA_BICLK3 0x44 52#define GOA_BICLK4 0x4F 53#define GOA_BICLK_OPT1 0x5B 54#define GOA_BICLK_OPT2 0x60 55#define MCS_GOA_GPO1 0x6D 56#define MCS_GOA_GPO2 0x71 57#define MCS_GOA_EQ 0x74 58#define MCS_GOA_CLK_GALLON 0x7C 59#define MCS_GOA_FS_SEL0 0x7E 60#define MCS_GOA_FS_SEL1 0x87 61#define MCS_GOA_FS_SEL2 0x91 62#define MCS_GOA_FS_SEL3 0x9B 63#define MCS_GOA_BS_SEL0 0xAC 64#define MCS_GOA_BS_SEL1 0xB5 65#define MCS_GOA_BS_SEL2 0xBF 66#define MCS_GOA_BS_SEL3 0xC9 67#define MCS_GOA_BS_SEL4 0xD3 68 69/* CMD2 P3 commands (Gamma) */ 70#define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */ 71#define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */ 72 73struct rm68200_panel_priv { 74 struct udevice *reg; 75 struct udevice *backlight; 76 struct gpio_desc reset; 77}; 78 79static const struct display_timing default_timing = { 80 .pixelclock.typ = 54000000, 81 .hactive.typ = 720, 82 .hfront_porch.typ = 48, 83 .hback_porch.typ = 48, 84 .hsync_len.typ = 9, 85 .vactive.typ = 1280, 86 .vfront_porch.typ = 12, 87 .vback_porch.typ = 12, 88 .vsync_len.typ = 5, 89}; 90 91static void rm68200_dcs_write_buf(struct udevice *dev, const void *data, 92 size_t len) 93{ 94 struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); 95 struct mipi_dsi_device *device = plat->device; 96 int err; 97 98 err = mipi_dsi_dcs_write_buffer(device, data, len); 99 if (err < 0) 100 dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err); 101} 102 103static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value) 104{ 105 struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); 106 struct mipi_dsi_device *device = plat->device; 107 int err; 108 109 err = mipi_dsi_dcs_write(device, cmd, &value, 1); 110 if (err < 0) 111 dev_err(dev, "MIPI DSI DCS write failed: %d\n", err); 112} 113 114#define dcs_write_seq(ctx, seq...) \ 115({ \ 116 static const u8 d[] = { seq }; \ 117 \ 118 rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ 119}) 120 121/* 122 * This panel is not able to auto-increment all cmd addresses so for some of 123 * them, we need to send them one by one... 124 */ 125#define dcs_write_cmd_seq(ctx, cmd, seq...) \ 126({ \ 127 static const u8 d[] = { seq }; \ 128 unsigned int i; \ 129 \ 130 for (i = 0; i < ARRAY_SIZE(d) ; i++) \ 131 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \ 132}) 133 134static void rm68200_init_sequence(struct udevice *dev) 135{ 136 /* Enter CMD2 with page 0 */ 137 dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P0); 138 dcs_write_cmd_seq(dev, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00); 139 dcs_write_seq(dev, MCS_BT2CTR, 0xE5); 140 dcs_write_seq(dev, MCS_SETAVDD, 0x0A); 141 dcs_write_seq(dev, MCS_SETAVEE, 0x0A); 142 dcs_write_seq(dev, MCS_SGOPCTR, 0x52); 143 dcs_write_seq(dev, MCS_BT3CTR, 0x53); 144 dcs_write_seq(dev, MCS_BT4CTR, 0x5A); 145 dcs_write_seq(dev, MCS_INVCTR, 0x00); 146 dcs_write_seq(dev, MCS_STBCTR, 0x0A); 147 dcs_write_seq(dev, MCS_SDCTR, 0x06); 148 dcs_write_seq(dev, MCS_VCMCTR, 0x56); 149 dcs_write_seq(dev, MCS_SETVGN, 0xA0, 0x00); 150 dcs_write_seq(dev, MCS_SETVGP, 0xA0, 0x00); 151 dcs_write_seq(dev, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */ 152 153 dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P2); 154 dcs_write_seq(dev, GOA_VSTV1, 0x05); 155 dcs_write_seq(dev, 0x02, 0x0B); 156 dcs_write_seq(dev, 0x03, 0x0F); 157 dcs_write_seq(dev, 0x04, 0x7D, 0x00, 0x50); 158 dcs_write_cmd_seq(dev, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00, 159 0x50); 160 dcs_write_cmd_seq(dev, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D, 161 0x00, 0x85, 0x08); 162 dcs_write_cmd_seq(dev, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D, 163 0x00, 0x85, 0x08); 164 dcs_write_seq(dev, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 165 0x00, 0x00, 0x00, 0x00); 166 dcs_write_cmd_seq(dev, GOA_BICLK1, 0x07, 0x08); 167 dcs_write_seq(dev, 0x2D, 0x01); 168 dcs_write_seq(dev, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D, 169 0x00); 170 dcs_write_cmd_seq(dev, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00); 171 dcs_write_seq(dev, 0x3D, 0x40); 172 dcs_write_seq(dev, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00); 173 dcs_write_seq(dev, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 174 0x00, 0x00, 0x00, 0x00, 0x00); 175 dcs_write_seq(dev, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 176 0x00, 0x00); 177 dcs_write_seq(dev, 0x58, 0x00, 0x00, 0x00); 178 dcs_write_seq(dev, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00); 179 dcs_write_seq(dev, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 181 dcs_write_seq(dev, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00); 182 dcs_write_seq(dev, MCS_GOA_GPO2, 0x00, 0x20, 0x00); 183 dcs_write_seq(dev, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 184 0x00, 0x00); 185 dcs_write_seq(dev, MCS_GOA_CLK_GALLON, 0x00, 0x00); 186 dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10, 187 0x16, 0x12, 0x08, 0x3F); 188 dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C, 189 0x0A, 0x0E, 0x3F, 0x3F, 0x00); 190 dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 191 0x05, 0x01, 0x3F, 0x3F, 0x0F); 192 dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F, 193 0x3F); 194 dcs_write_cmd_seq(dev, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15); 195 dcs_write_cmd_seq(dev, 0xA9, 0x07, 0x03, 0x3F); 196 dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13, 197 0x15, 0x11, 0x0F, 0x3F); 198 dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B, 199 0x0D, 0x09, 0x3F, 0x3F, 0x07); 200 dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F, 201 0x02, 0x06, 0x3F, 0x3F, 0x08); 202 dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F, 203 0x3F, 0x3F, 0x0E, 0x10, 0x14); 204 dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F); 205 dcs_write_seq(dev, 0xDC, 0x02); 206 dcs_write_seq(dev, 0xDE, 0x12); 207 208 dcs_write_seq(dev, MCS_CMD_MODE_SW, 0x0E); /* No documentation */ 209 dcs_write_seq(dev, 0x01, 0x75); 210 211 dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P3); 212 dcs_write_cmd_seq(dev, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06, 213 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, 214 0x12, 0x0C, 0x00); 215 dcs_write_cmd_seq(dev, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06, 216 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, 217 0x12, 0x0C, 0x00); 218 219 /* Exit CMD2 */ 220 dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD1_UCS); 221} 222 223static int rm68200_panel_enable_backlight(struct udevice *dev) 224{ 225 struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); 226 struct mipi_dsi_device *device = plat->device; 227 struct rm68200_panel_priv *priv = dev_get_priv(dev); 228 int ret; 229 230 ret = mipi_dsi_attach(device); 231 if (ret < 0) 232 return ret; 233 234 rm68200_init_sequence(dev); 235 236 ret = mipi_dsi_dcs_exit_sleep_mode(device); 237 if (ret) 238 return ret; 239 240 mdelay(125); 241 242 ret = mipi_dsi_dcs_set_display_on(device); 243 if (ret) 244 return ret; 245 246 mdelay(20); 247 248 ret = backlight_enable(priv->backlight); 249 if (ret) 250 return ret; 251 252 return 0; 253} 254 255static int rm68200_panel_get_display_timing(struct udevice *dev, 256 struct display_timing *timings) 257{ 258 memcpy(timings, &default_timing, sizeof(*timings)); 259 260 return 0; 261} 262 263static int rm68200_panel_of_to_plat(struct udevice *dev) 264{ 265 struct rm68200_panel_priv *priv = dev_get_priv(dev); 266 int ret; 267 268 if (CONFIG_IS_ENABLED(DM_REGULATOR)) { 269 ret = device_get_supply_regulator(dev, "power-supply", 270 &priv->reg); 271 if (ret && ret != -ENOENT) { 272 dev_err(dev, "Warning: cannot get power supply\n"); 273 return ret; 274 } 275 } 276 277 ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, 278 GPIOD_IS_OUT); 279 if (ret) { 280 dev_err(dev, "Warning: cannot get reset GPIO\n"); 281 if (ret != -ENOENT) 282 return ret; 283 } 284 285 ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, 286 "backlight", &priv->backlight); 287 if (ret) { 288 dev_err(dev, "Cannot get backlight: ret=%d\n", ret); 289 return ret; 290 } 291 292 return 0; 293} 294 295static int rm68200_panel_probe(struct udevice *dev) 296{ 297 struct rm68200_panel_priv *priv = dev_get_priv(dev); 298 struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); 299 int ret; 300 301 if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->reg) { 302 ret = regulator_set_enable(priv->reg, true); 303 if (ret) 304 return ret; 305 } 306 307 /* reset panel */ 308 dm_gpio_set_value(&priv->reset, true); 309 mdelay(1); 310 dm_gpio_set_value(&priv->reset, false); 311 mdelay(10); 312 313 /* fill characteristics of DSI data link */ 314 plat->lanes = 2; 315 plat->format = MIPI_DSI_FMT_RGB888; 316 plat->mode_flags = MIPI_DSI_MODE_VIDEO | 317 MIPI_DSI_MODE_VIDEO_BURST | 318 MIPI_DSI_MODE_LPM; 319 320 return 0; 321} 322 323static const struct panel_ops rm68200_panel_ops = { 324 .enable_backlight = rm68200_panel_enable_backlight, 325 .get_display_timing = rm68200_panel_get_display_timing, 326}; 327 328static const struct udevice_id rm68200_panel_ids[] = { 329 { .compatible = "raydium,rm68200" }, 330 { } 331}; 332 333U_BOOT_DRIVER(rm68200_panel) = { 334 .name = "rm68200_panel", 335 .id = UCLASS_PANEL, 336 .of_match = rm68200_panel_ids, 337 .ops = &rm68200_panel_ops, 338 .of_to_plat = rm68200_panel_of_to_plat, 339 .probe = rm68200_panel_probe, 340 .plat_auto = sizeof(struct mipi_dsi_panel_plat), 341 .priv_auto = sizeof(struct rm68200_panel_priv), 342}; 343