#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
215a0656 |
|
13-Aug-2018 |
Marek Vasut <marex@denx.de> |
net: designware: socfpga: Add Arria10 extras Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com> |
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
215a0656 |
|
13-Aug-2018 |
Marek Vasut <marex@denx.de> |
net: designware: socfpga: Add Arria10 extras Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com> |
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
a90ae016 |
|
24-Dec-2020 |
Chee Hong Ang <chee.hong.ang@intel.com> |
net: designware: socfpga: Add ATF support for MAC driver In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
|
13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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4f1267ce |
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13-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
net: designware: socfpga: adapt to Gen5 This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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215a0656 |
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13-Aug-2018 |
Marek Vasut <marex@denx.de> |
net: designware: socfpga: Add Arria10 extras Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
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