Searched refs:reset (Results 151 - 175 of 530) sorted by relevance

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/u-boot/drivers/reset/
H A Dreset-hsdk.c15 #include <reset-uclass.h>
59 /* wait till reset bit is back to 0 */
84 { .compatible = "snps,hsdk-reset" },
104 .name = "hsdk-reset",
H A Dreset-meson.c13 #include <reset-uclass.h>
88 .compatible = "amlogic,meson-gxbb-reset",
92 .compatible = "amlogic,meson-axg-reset",
96 .compatible = "amlogic,meson-a1-reset",
H A Dreset-mediatek.c15 #include <reset-uclass.h>
76 ret = device_bind_driver_to_node(pdev, "mediatek_reset", "reset",
H A Dreset-dra7.c3 * Texas Instruments DRA7 reset driver
12 #include <reset-uclass.h>
61 { .compatible = "ti,dra7-reset" },
73 dev_info(dev, "dra7-reset successfully probed %s\n", dev->name);
/u-boot/drivers/video/
H A Dhimax-hx8394.c18 struct gpio_desc reset; member in struct:hx8394_panel_priv
93 /* Panel is operational 120 msec after reset */
171 ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
174 dev_err(dev, "warning: cannot get reset GPIO (%d)\n", ret);
188 dm_gpio_set_value(&priv->reset, true);
205 dm_gpio_set_value(&priv->reset, false);
/u-boot/drivers/i2c/
H A Dast2600_i2c.c13 #include <reset.h>
308 struct reset_ctl reset; member in struct:ast2600_i2c_global_priv
341 ret = reset_get_by_index(dev, 0, &i2c_global->reset);
343 printf("%s(): Failed to get reset signal\n", __func__);
347 reset_deassert(&i2c_global->reset);
/u-boot/board/logicpd/am3517evm/
H A Dam3517evm.c79 .reset = am35x_musb_reset,
/u-boot/drivers/clk/sunxi/
H A Dclk_a10s.c13 #include <dt-bindings/reset/sun5i-ccu.h>
H A Dclk_v3s.c13 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
/u-boot/cmd/
H A D2048.c41 char color[40], reset[] = "\033[0m"; local
51 printf("%s", reset);
67 printf("%s", reset);
74 printf("%s", reset);
/u-boot/drivers/watchdog/
H A Dast2600_wdt.c84 .reset = ast2600_wdt_reset,
H A Dbcm6345_wdt.c79 .reset = bcm6345_wdt_reset,
H A Dat91sam9_wdt.c64 priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
96 .reset = at91_wdt_reset,
H A Dftwdt010_wdt.c68 * the reset timer is 1 second.
117 .reset = ftwdt010_wdt_reset,
H A Dsbsa_gwdt.c114 .reset = sbsa_gwdt_reset,
H A Dsl28cpld-wdt.c49 /* (3) kick it, will reset timer to the timeout value */
94 .reset = sl28cpld_wdt_reset,
/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dcpu_init.c155 gd->arch.reset_status = __raw_readl(&im->reset.rsr);
156 __raw_writel(~(RSR_RES), &im->reset.rsr);
164 * contains checkstop reset enable (4.6.1.4)
166 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
372 * Figure out the cause of the reset
/u-boot/board/freescale/ls1012aqds/
H A Deth.c88 if (priv->realbus->reset)
89 return priv->realbus->reset(priv->realbus);
113 bus->reset = ls1012aqds_mdio_reset;
/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c43 * reset controls for core 3. The secondary core entry address register
51 * R528 is also different, as it has both cores powered up (but held in reset
52 * state) after the SoC is reset. Like the R40, it uses a "soft" entry point
149 /* R528 leaves both cores powered up, manages them via reset */
176 static void __secure sunxi_cpu_set_reset(int cpu, bool reset) argument
179 if (reset)
189 writel(reset ? 0b00 : 0b11, SUNXI_CPUCFG_BASE + SUNXI_CPU_RST(cpu));
234 /* Assert reset on target CPU */
309 /* Assert reset on target CPU */
321 /* De-assert reset o
[all...]
/u-boot/net/
H A Dmdio-uclass.c99 if (!ops->reset)
102 return ops->reset(mdio_dev);
106 * Following read/write/reset functions are registered with legacy MII code.
176 pdata->mii_bus->reset = mdio_reset;
181 /* Get bus level PHY reset GPIO details */
182 mii_bus->reset_delay_us = dev_read_u32_default(dev, "reset-delay-us",
185 "reset-post-delay-us",
187 ret = gpio_request_by_name(dev, "reset-gpios", 0, &mii_bus->reset_gpiod,
190 dev_err(dev, "couldn't get reset-gpios: %d\n", ret);
/u-boot/drivers/net/
H A Dbcm6348-eth.c18 #include <reset.h>
140 /* reset emac */
144 /* wait until emac is reset */
464 struct reset_ctl reset; local
467 ret = reset_get_by_index(dev, i, &reset);
471 ret = reset_deassert(&reset);
473 pr_err("%s: error deasserting reset %d\n", __func__, i);
477 ret = reset_free(&reset);
479 pr_err("%s: error freeing reset %d\n", __func__, i);
487 /* reset ema
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/u-boot/test/dm/
H A Dscmi.c18 #include <reset.h>
46 ut_assertnonnull(agent->reset);
195 /* reset agent configuration */
279 /* scmi reset */
280 ut_assert(run_command("scmi reset 1 1", 0));
481 /* Sandbox SCMI reset protocol doesn't have its own channel */
490 ut_assert(!agent->reset[0].asserted);
492 ut_assertok(reset_assert(&scmi_devices->reset[0]));
493 ut_assert(agent->reset[0].asserted);
495 ut_assertok(reset_deassert(&scmi_devices->reset[
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/u-boot/drivers/remoteproc/
H A Dti_k3_r5f_rproc.c17 #include <reset.h>
88 * @reset: reset control handle
101 struct reset_ctl reset; member in struct:k3_r5f_core
176 /* deassert local reset on all applicable cores */
178 ret = reset_deassert(&cluster->cores[c]->reset);
187 reset_assert(&cluster->cores[c]->reset);
208 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
213 ret = reset_deassert(&core->reset);
215 dev_err(core->dev, "local-reset deasser
[all...]
/u-boot/drivers/net/octeontx/
H A Dq_struct.h597 u64 reset:1; member in struct:cq_cfg
611 u64 reset:1;
622 u64 reset:1; member in struct:sq_cfg
634 u64 reset:1;
645 u64 reset:1; member in struct:rbdr_cfg
661 u64 reset:1;
/u-boot/lib/acpi/
H A Dacpi_device.c401 struct acpi_gpio reset, enable, stop; local
405 gpio_get_acpi(reset_gpio, &reset);
408 has_reset = reset.pins[0];
426 dw0_write, &reset, true);
440 dw0_write, &reset, false);
468 dw0_write, &reset, true);

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