/u-boot/arch/x86/dts/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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/u-boot/arch/sandbox/dts/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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/u-boot/dts/upstream/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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H A D | rzv2m-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin))
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/u-boot/drivers/net/fm/ |
H A D | t1040.c | 12 phy_interface_t fman_port_enet_if(enum fm_port port) argument 18 if ((port == FM1_DTSEC2) && 29 if ((port == FM1_DTSEC4) && 40 if (port == FM1_DTSEC5) { 46 switch (port) { 49 if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || 50 is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) 55 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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H A D | ls1043.c | 36 static int is_device_disabled(enum fm_port port) argument 41 return port_to_devdisr[port] & devdisr2; 44 void fman_disable_port(enum fm_port port) argument 48 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 51 phy_interface_t fman_port_enet_if(enum fm_port port) argument 56 if (is_device_disabled(port)) 59 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) 62 if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) 65 if (port == FM1_DTSEC3) 70 if (port [all...] |
H A D | t2080.c | 29 static int is_device_disabled(enum fm_port port) argument 34 return port_to_devdisr[port] & devdisr2; 37 void fman_disable_port(enum fm_port port) argument 41 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 44 phy_interface_t fman_port_enet_if(enum fm_port port) argument 49 if (is_device_disabled(port)) 52 if ((port == FM1_10GEC1 || port == FM1_10GEC2) && 58 if ((port == FM1_10GEC3 || port [all...] |
H A D | p1023.c | 17 static int is_device_disabled(enum fm_port port) argument 22 return port_to_devdisr[port] & devdisr; 25 void fman_disable_port(enum fm_port port) argument 30 if (port == FM1_DTSEC1) 33 setbits_be32(&gur->devdisr, port_to_devdisr[port]); 36 void fman_enable_port(enum fm_port port) argument 40 clrbits_be32(&gur->devdisr, port_to_devdisr[port]); 43 phy_interface_t fman_port_enet_if(enum fm_port port) argument 48 if (is_device_disabled(port)) 52 if (port [all...] |
H A D | b4860.c | 26 static int is_device_disabled(enum fm_port port) argument 31 return port_to_devdisr[port] & devdisr2; 34 void fman_disable_port(enum fm_port port) argument 38 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 41 void fman_enable_port(enum fm_port port) argument 45 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 48 phy_interface_t fman_port_enet_if(enum fm_port port) argument 57 if (is_device_disabled(port)) 61 if ((port == FM1_10GEC1 || port [all...] |
/u-boot/arch/arm/include/asm/mach-imx/ |
H A D | gpio.h | 20 #define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
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/u-boot/dts/upstream/include/dt-bindings/gpio/ |
H A D | tegra241-gpio.h | 32 #define TEGRA241_MAIN_GPIO(port, offset) \ 33 ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset)) 39 #define TEGRA241_AON_GPIO(port, offset) \ 40 ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset))
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/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | qe_io.c | 16 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) argument 33 in_be32(&par_io[port].cpdir2) : 34 in_be32(&par_io[port].cpdir1); 37 out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val); 38 out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val); 40 out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val); 41 out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); 48 tmp_val = in_be32(&par_io[port].cpodr); 50 out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val); 52 out_be32(&par_io[port] [all...] |
/u-boot/arch/mips/mach-jz47xx/jz4780/ |
H A D | gpio.c | 11 int port = gpio / 32; local 14 return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin); 20 int port = gpio / 32; local 23 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); 24 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); 25 writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port)); 31 int port = gpio / 32; local 34 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); 35 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); 36 writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port)); [all...] |
/u-boot/drivers/bios_emulator/ |
H A D | biosemui.h | 89 Function codes passed to the emulated I/O port functions to determine the 103 Function codes passed to the emulated I/O port functions to determine the 121 type - Type of port access (1 = byte, 2 = word, 3 = dword) 131 #define PM_inpb(port) inb(port) 132 #define PM_inpw(port) inw(port) 133 #define PM_inpd(port) inl(port) 134 #define PM_outpb(port, va [all...] |
H A D | besys.c | 44 * timer port access. Made all the VGA port except reading 0x3c3 46 * 16 bit of the io port. 245 /* For Non-Intel machines we may need to emulate some I/O port accesses that 249 #define IS_TIMER_PORT(port) (0x40 <= port && port <= 0x43) 250 #define IS_CMOS_PORT(port) (0x70 <= port && port < 267 VGA_inpb(const int port) argument 343 VGA_outpb(int port, u8 val) argument 501 PCI_inp(int port, int type) argument 532 PCI_outp(int port, u32 val, int type) argument 570 BE_inb(X86EMU_pioAddr port) argument 616 BE_inw(X86EMU_pioAddr port) argument 649 BE_inl(X86EMU_pioAddr port) argument 679 BE_outb(X86EMU_pioAddr port, u8 val) argument 714 BE_outw(X86EMU_pioAddr port, u16 val) argument 745 BE_outl(X86EMU_pioAddr port, u32 val) argument [all...] |
/u-boot/arch/xtensa/include/asm/ |
H A D | io.h | 59 #define inb(port) readb((u8 *)((port))) 60 #define outb(val, port) writeb((val), (u8 *)((unsigned long)(port))) 61 #define inw(port) readw((u16 *)((port))) 62 #define outw(val, port) writew((val), (u16 *)((unsigned long)(port))) 63 #define inl(port) readl((u32 *)((port))) [all...] |
/u-boot/drivers/pci/ |
H A D | pcie_mediatek.c | 32 /* PCIe per port registers */ 60 /* PCIe V2 per-port registers */ 178 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) argument 183 err = readl_poll_timeout(port->base + PCIE_APP_TLP_REQ, val, 188 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 194 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn, argument 200 port->base + PCIE_CFG_HEADER0); 201 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 203 port->base + PCIE_CFG_HEADER2); 206 tmp = readl(port 225 mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn, int where, int size, u32 val) argument 252 struct mtk_pcie_port *port; local 286 struct mtk_pcie_port *port; local 306 struct mtk_pcie_port *port; local 324 mtk_pcie_port_free(struct mtk_pcie_port *port) argument 330 mtk_pcie_startup_port(struct mtk_pcie_port *port) argument 373 mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) argument 440 mtk_pcie_enable_port(struct mtk_pcie_port *port) argument 479 mtk_pcie_enable_port_v2(struct mtk_pcie_port *port) argument 531 struct mtk_pcie_port *port; local 569 struct mtk_pcie_port *port; local 638 struct mtk_pcie_port *port, *tmp; local 685 struct mtk_pcie_port *port, *tmp; local [all...] |
/u-boot/arch/m68k/include/asm/ |
H A D | io.h | 46 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) 47 #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) 48 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) 49 #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) 50 #define insl(port, buf, nl) _insl_ns((u32 *)((port) 69 _insb(volatile u8 * port, void *buf, int ns) argument 76 _outsb(volatile u8 * port, const void *buf, int ns) argument 83 _insw(volatile u16 * port, void *buf, int ns) argument 90 _outsw(volatile u16 * port, const void *buf, int ns) argument 99 _insl(volatile u32 * port, void *buf, int nl) argument 106 _outsl(volatile u32 * port, const void *buf, int nl) argument 115 _insw_ns(volatile u16 * port, void *buf, int ns) argument 122 _outsw_ns(volatile u16 * port, const void *buf, int ns) argument 130 _insl_ns(volatile u32 * port, void *buf, int nl) argument 137 _outsl_ns(volatile u32 * port, const void *buf, int nl) argument [all...] |
/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
H A D | board_env_spec.h | 130 #define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000) 132 #define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804) 133 #define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C) 134 #define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918) 135 #define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) [all...] |
/u-boot/drivers/misc/ |
H A D | winbond_w83627.c | 13 /* Enable configuration: pass entry key '0x87' into index port dev twice */ 16 u16 port = dev >> 8; local 18 outb(WINBOND_ENTRY_KEY, port); 19 outb(WINBOND_ENTRY_KEY, port); 22 /* Disable configuration: pass exit key '0xAA' into index port dev */ 25 u16 port = dev >> 8; local 27 outb(WINBOND_EXIT_KEY, port);
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/u-boot/drivers/serial/ |
H A D | serial_ns16550.c | 24 #error "Console port 1 defined but not configured." 26 #error "Console port 2 defined but not configured." 28 #error "Console port 3 defined but not configured." 30 #error "Console port 4 defined but not configured." 32 #error "Console port 5 defined but not configured." 34 #error "Console port 6 defined but not configured." 37 /* Note: The port number specified in the functions is 1 based. 73 #define PORT serial_ports[port-1] 76 #define DECLARE_ESERIAL_FUNCTIONS(port) \ 77 static int eserial##port##_ini 118 _serial_putc(const char c, const int port) argument 126 _serial_puts(const char *s, const int port) argument 133 _serial_getc(const int port) argument 138 _serial_tstc(const int port) argument 143 _serial_setbrg(const int port) argument [all...] |
/u-boot/arch/x86/cpu/quark/ |
H A D | msg_port.c | 11 void msg_port_setup(int op, int port, int reg) argument 14 (((op) << 24) | ((port) << 16) | 18 u32 msg_port_read(u8 port, u32 reg) argument 24 msg_port_setup(MSG_OP_READ, port, reg); 30 void msg_port_write(u8 port, u32 reg, u32 value) argument 35 msg_port_setup(MSG_OP_WRITE, port, reg); 38 u32 msg_port_alt_read(u8 port, u32 reg) argument 44 msg_port_setup(MSG_OP_ALT_READ, port, reg); 50 void msg_port_alt_write(u8 port, u32 reg, u32 value) argument 55 msg_port_setup(MSG_OP_ALT_WRITE, port, re 58 msg_port_io_read(u8 port, u32 reg) argument 70 msg_port_io_write(u8 port, u32 reg, u32 value) argument [all...] |
/u-boot/arch/mips/mach-octeon/ |
H A D | cvmx-helper-agl.c | 47 * Convert interface to port to assess CSRs. 50 * @return The port corresponding to the interface 73 int port = cvmx_helper_agl_get_port(interface); local 86 printf("Management port AGL failed BIST (0x%016llx) on AGL%d\n", 87 CAST64(gmx_bist.u64), port); 90 gmx_prtx_cfg.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port)); 92 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), gmx_prtx_cfg.u64); 99 agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port)); 109 cvmx_helper_get_agl_refclk_sel(interface, port); 111 cvmx_helper_get_agl_rx_clock_skew(interface, port); 166 int port = cvmx_helper_agl_get_port(interface); local 228 int port = cvmx_helper_agl_get_port(interface); local [all...] |
/u-boot/arch/powerpc/cpu/mpc83xx/ |
H A D | qe_io.c | 19 * @port: io pin port 29 static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir, argument 47 in_be32(&par_io->ioport[port].dir2) : 48 in_be32(&par_io->ioport[port].dir1); 51 out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val); 52 out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val); 54 out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val); 55 out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val); 62 tmp_val = in_be32(&par_io->ioport[port] 97 qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) argument [all...] |
/u-boot/drivers/usb/host/ |
H A D | ehci-mxs.c | 34 static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) argument 43 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 44 writel(port->pll_en_bits, (u32)port->pll + pll_offset); 48 writel(port->pll_dis_bits, (u32)port->pll + pll_offset); 49 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 55 static int __ehci_hcd_init(struct ehci_mxs_port *port, enum usb_init_type init, argument 62 writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set); 65 &port 88 __ehci_hcd_stop(struct ehci_mxs_port *port) argument 119 struct ehci_mxs_port port; member in struct:ehci_mxs_priv_data 137 struct ehci_mxs_port *port = &priv->port; local 219 struct ehci_mxs_port *port = &priv->port; local 259 struct ehci_mxs_port *port = &priv->port; local [all...] |