Searched refs:opcode (Results 26 - 50 of 83) sorted by relevance

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/u-boot/include/
H A Dspi-mem.h21 .opcode = __opcode, \
75 * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is
78 * @cmd.opcode: operation opcode
79 * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
88 * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
103 u16 opcode; member in struct:spi_mem_op::__anon2
H A Dmmc.h328 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
493 * @opcode: Command opcode to send
496 int (*execute_tuning)(struct udevice *dev, uint opcode);
553 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
799 int mmc_send_tuning(struct mmc *mmc, u32 opcode);
/u-boot/arch/x86/cpu/
H A Dmtrr.c266 * @opcode: Indicates operation to perform
273 enum mtrr_opcode opcode; member in struct:mtrr_oper
285 switch (oper->opcode) {
319 oper.opcode = MTRR_OP_SET_VALID;
330 oper.opcode = MTRR_OP_SET;
/u-boot/drivers/mmc/
H A Dsdhci-cadence.c205 unsigned int opcode)
222 if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
227 mmc_send_tuning(mmc, opcode)) { /* bad */
204 sdhci_cdns_execute_tuning(struct udevice *dev, unsigned int opcode) argument
H A Dmmc-uclass.c116 static int dm_mmc_execute_tuning(struct udevice *dev, uint opcode) argument
122 return ops->execute_tuning(dev, opcode);
125 int mmc_execute_tuning(struct mmc *mmc, uint opcode) argument
130 ret = dm_mmc_execute_tuning(mmc->dev, opcode);
H A Docteontx_hsmmc.c1635 static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp) argument
1642 debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
1643 cmd.cmdidx = opcode;
1650 mmc->dev->name, opcode, err);
1656 static int octeontx_mmc_send_tuning(struct mmc *mmc, u32 opcode, int *error) argument
1659 return mmc_send_tuning(mmc, opcode);
1662 static int octeontx_mmc_test_get_ext_csd(struct mmc *mmc, u32 opcode, argument
1670 debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
2003 int (*test)(struct mmc *mmc, u32 opcode, int *error);
2004 u32 opcode; member in struct:adj
2032 octeontx_mmc_adjust_tuning(struct mmc *mmc, struct adj *adj, u32 opcode) argument
2270 octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode) argument
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H A Drockchip_sdhci.c488 static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) argument
504 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
509 cmd.cmdidx = opcode;
/u-boot/drivers/ufs/
H A Dufs.c773 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
783 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) {
918 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
995 enum query_opcode opcode,
1002 (*request)->upiu_req.opcode = opcode;
1011 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, argument
1019 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1022 switch (opcode) {
1040 "%s: Expected query flag opcode bu
992 ufshcd_init_query(struct ufs_hba *hba, struct ufs_query_req **request, struct ufs_query_res **response, enum query_opcode opcode, u8 idn, u8 index, u8 selector) argument
1063 ufshcd_query_flag_retry(struct ufs_hba *hba, enum query_opcode opcode, enum flag_idn idn, bool *flag_res) argument
1087 __ufshcd_query_descriptor(struct ufs_hba *hba, enum query_opcode opcode, enum desc_idn idn, u8 index, u8 selector, u8 *desc_buf, int *buf_len) argument
1147 ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, enum desc_idn idn, u8 index, u8 selector, u8 *desc_buf, int *buf_len) argument
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/u-boot/drivers/mtd/spi/
H A Dspi-nor-core.c171 #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
218 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
226 * Return: The opcode extension.
233 return ~op->cmd.opcode;
236 return op->cmd.opcode;
282 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
314 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) argument
316 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),
604 static u8 spi_nor_convert_opcode(u8 opcode, cons argument
616 spi_nor_convert_3to4_read(u8 opcode) argument
637 spi_nor_convert_3to4_program(u8 opcode) argument
651 spi_nor_convert_3to4_erase(u8 opcode) argument
2040 spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, u8 opcode, enum spi_nor_protocol proto) argument
2053 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, enum spi_nor_protocol proto) argument
2384 u8 opcode; local
2516 u32 *table, opcode, addr; local
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H A Dsf_dataflash.c85 u8 opcode = OP_READ_STATUS; local
90 * a dummy byte after the opcode...
92 ret = spi_write_then_read(spi, &opcode, 1, NULL, &status, 1);
562 u8 opcode = CMD_READ_ID; local
573 tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, id_size);
/u-boot/drivers/nvme/
H A Dnvme_apple.c51 u8 opcode; member in struct:ans_nvmmu_tcb
121 tcb->opcode = cmd->common.opcode;
H A Dnvme.c271 static int nvme_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) argument
276 c.delete_queue.opcode = opcode;
423 c.create_cq.opcode = nvme_admin_create_cq;
440 c.create_sq.opcode = nvme_admin_create_sq;
460 c.identify.opcode = nvme_admin_identify;
492 c.features.opcode = nvme_admin_get_features;
519 c.features.opcode = nvme_admin_set_features;
765 c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;
/u-boot/include/linux/mtd/
H A Dspi-nor.h19 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
35 * Note on opcode nomenclature: some opcodes have a format like
37 * of I/O lines used for the opcode, address, and data (respectively). The
38 * FUNCTION has an optional suffix of '4', to represent an opcode which
127 #define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */
143 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
384 u8 opcode; member in struct:spi_nor_read_command
389 u8 opcode; member in struct:spi_nor_pp_command
451 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
454 * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode
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/u-boot/drivers/spi/
H A Dmicrochip_coreqspi.c310 u8 opcode = op->cmd.opcode; local
323 if (op->cmd.opcode) {
324 qspi->txbuf = &opcode;
H A Dmtk_snor.c217 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(4));
222 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(3));
226 if (op->cmd.opcode == 0x0b)
404 txbuf[tx_cnt] = op->cmd.opcode;
446 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA0);
H A Dspi-sifive.c277 u8 opcode = op->cmd.opcode; local
289 /* send the opcode */
290 ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
292 dev_err(dev, "failed to xfer opcode\n");
H A Dti_qspi.c287 u8 opcode, u8 data_nbits, u8 addr_width,
290 u32 memval = opcode;
348 ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
286 ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs, u8 opcode, u8 data_nbits, u8 addr_width, u8 dummy_bytes) argument
H A Docteon_spi.c440 u8 opcode, *buf; local
449 opcode = op->cmd.opcode;
454 ret = octeontx2_spi_xfer(slave->dev, 8, (void *)&opcode, NULL, flags);
H A Dspi-mem-nodm.c38 op_buf[pos++] = op->cmd.opcode;
51 /* 1st transfer: opcode + address + dummy cycles */
H A Dnpcm_fiu_spi.c238 debug("fiu_uma: opcode 0x%x, dir %d, addr 0x%x, %d bytes\n",
239 op->cmd.opcode, op->data.dir, addr, nbytes);
249 writel(op->cmd.opcode, &regs->uma_cmd);
H A Dspi-uclass.c154 int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, argument
164 ret = spi_xfer(slave, n_opcode * 8, opcode, NULL, flags);
H A Dstm32_qspi.c248 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
265 ccr |= op->cmd.opcode;
H A Dxilinx_spi.c337 if (op->cmd.opcode) {
338 ret = start_transfer(spi->dev, (void *)&op->cmd.opcode,
/u-boot/drivers/mtd/nand/raw/
H A Docteontx_nand.c39 * Commands are selected by the 4 bit opcode.
87 #define NDF_OP_WAIT_STATUS 0xb /* same opcode for WAIT_STATUS_ALE */
96 u16 opcode: 4; member in struct:ndf_nop_cmd
101 u16 opcode:4; member in struct:ndf_wait_cmd
109 u16 opcode:4; member in struct:ndf_bus_cmd
115 u16 opcode:4; member in struct:ndf_chip_cmd
123 u32 opcode:4; member in struct:ndf_cle_cmd
134 u32 opcode:4; member in struct:ndf_rd_cmd
143 u32 opcode:4; member in struct:ndf_wr_cmd
152 u64 opcode member in struct:ndf_set_tm_par_cmd
164 u32 opcode:4; member in struct:ndf_ale_cmd
184 u32 opcode:4; member in struct:ndf_wait_status_cmd
624 int opcode = cmd->val[0] & 0xf; local
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/u-boot/arch/arm/include/asm/
H A Dopcodes.h11 extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
20 * Assembler opcode byteswap helpers.
160 * In rare cases it is necessary to assemble an opcode which the
174 * __inst_arm(x): emit the specified ARM opcode
175 * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
176 * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
179 * 16-bit Thumb opcode, depending on whether an ARM or Thumb-2
183 * 32-bit Thumb opcode, depending on whether an ARM or Thumb-2
192 * that the correct opcode gets emitted depending on the instruction set

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