/u-boot/include/ |
H A D | sandbox-clk.h | 10 #include <linux/clk-provider.h> 31 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name, 35 static inline struct clk *sandbox_clk_fixed_factor(const char *name, 44 static inline struct clk *sandbox_clk_divider(const char *name, 53 static inline struct clk *sandbox_clk_gate(const char *name, const char *parent, 61 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name, 67 static inline struct clk *sandbox_clk_gate2(const char *name, 76 static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg, 86 int sandbox_clk_enable_count(struct clk *clk); [all...] |
/u-boot/board/samsung/trats/ |
H A D | trats.c | 48 struct exynos4_clock *clk = local 62 writel(0xa0c80604, &clk->apll_con0); 69 writel(0x00000100, &clk->div_cpu0); 72 while (readl(&clk->div_stat_cpu0) & 0x1111111) 80 writel(0x13113117, &clk->div_dmc0); 83 while (readl(&clk->div_stat_dmc0) & 0x11111111) 96 writel(0x0, &clk->gate_ip_cam); /* CAM */ 97 writel(0x0, &clk->gate_ip_tv); /* TV */ 98 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 99 writel(0x0, &clk 312 struct exynos4_clock *clk = local [all...] |
/u-boot/drivers/clk/ |
H A D | ics8n3qv01.c | 14 #include <clk-uclass.h> 110 static ulong ics8n3qv01_set_rate(struct clk *clk, ulong fout) argument 112 struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev); 124 res = ics8n3qv01_get_fout_calc(clk->dev, 1, &fout_calc); 128 clk->dev->name); 134 printf("%s: PLL is off by %lld ppm\n", clk->dev->name, off_ppm); 141 clk->dev->name); 146 tmp = dm_i2c_reg_read(clk->dev, 0) & 0xc0; 163 tmp = dm_i2c_reg_read(clk 183 ics8n3qv01_get_rate(struct clk *clk) argument 190 ics8n3qv01_enable(struct clk *clk) argument 195 ics8n3qv01_disable(struct clk *clk) argument [all...] |
H A D | clk-divider.c | 17 #include <clk-uclass.h> 26 #include <linux/clk-provider.h> 30 #include <clk.h> 32 #include "clk.h" 61 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate, 79 static ulong clk_divider_recalc_rate(struct clk *clk) argument 81 struct clk_divider *divider = to_clk_divider(clk); 82 unsigned long parent_rate = clk_get_parent_rate(clk); 93 return divider_recalc_rate(clk, parent_rat 158 clk_divider_set_rate(struct clk *clk, unsigned long rate) argument 193 struct clk *clk; local 236 struct clk *clk; local [all...] |
H A D | clk_sandbox_test.c | 8 #include <clk.h> 10 #include <asm/clk.h> 39 struct clk *clk; local 41 clk = devm_clk_get(dev, "no-an-existing-clock"); 42 if (!IS_ERR(clk)) { 47 clk = devm_clk_get(dev, "uart2"); 48 if (IS_ERR(clk)) 49 return PTR_ERR(clk); 50 sbct->clkps[SANDBOX_CLK_TEST_ID_DEVM1] = clk; [all...] |
/u-boot/arch/mips/mach-mtmips/mt7628/ |
H A D | init.c | 8 #include <clk.h> 12 #include <dt-bindings/clock/mt7628-clk.h> 25 /* We can't use the clk driver as the DM has not been initialized yet */ 53 struct clk clk; local 85 clk.dev = clkdev; 87 clk.id = CLK_CPU; 88 cpu_clk = clk_get_rate(&clk); 90 clk.id = CLK_SYS; 91 bus_clk = clk_get_rate(&clk); [all...] |
/u-boot/drivers/clk/meson/ |
H A D | gxbb.c | 12 #include <clk-uclass.h> 76 static ulong meson_div_get_rate(struct clk *clk, unsigned long id); 77 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, 79 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id, 81 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id); 82 static ulong meson_clk_set_rate_by_id(struct clk *cl 198 meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on) argument 237 meson_clk_enable(struct clk *clk) argument 242 meson_clk_disable(struct clk *clk) argument 271 meson_div_get_rate(struct clk *clk, unsigned long id) argument 318 meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, ulong current_rate) argument 447 meson_mux_get_parent(struct clk *clk, unsigned long id) argument 492 meson_mux_set_parent(struct clk *clk, unsigned long id, unsigned long parent_id) argument 560 meson_mux_get_rate(struct clk *clk, unsigned long id) argument 570 meson_clk81_get_rate(struct clk *clk) argument 641 meson_mpll_get_rate(struct clk *clk, unsigned long id) argument 691 meson_pll_get_rate(struct clk *clk, unsigned long id) argument 726 meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) argument 800 meson_clk_get_rate(struct clk *clk) argument 805 meson_clk_set_parent(struct clk *clk, struct clk *parent) argument 810 meson_clk_set_rate_by_id(struct clk *clk, unsigned long id, ulong rate, ulong current_rate) argument 863 meson_clk_set_rate(struct clk *clk, ulong rate) argument [all...] |
/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3308.c | 7 #include <clk-uclass.h> 178 static ulong rk3308_i2c_get_clk(struct clk *clk) argument 180 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); 184 switch (clk->id) { 208 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz) argument 210 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); 217 switch (clk->id) { 239 return rk3308_i2c_get_clk(clk); 242 rk3308_mac_set_clk(struct clk *clk, uint hz) argument 272 rk3308_mac_set_speed_clk(struct clk *clk, uint hz) argument 288 rk3308_mmc_get_clk(struct clk *clk) argument 318 rk3308_mmc_set_clk(struct clk *clk, ulong set_rate) argument 360 rk3308_saradc_get_clk(struct clk *clk) argument 372 rk3308_saradc_set_clk(struct clk *clk, uint hz) argument 388 rk3308_tsadc_get_clk(struct clk *clk) argument 400 rk3308_tsadc_set_clk(struct clk *clk, uint hz) argument 416 rk3308_spi_get_clk(struct clk *clk) argument 443 rk3308_spi_set_clk(struct clk *clk, uint hz) argument 475 rk3308_pwm_get_clk(struct clk *clk) argument 487 rk3308_pwm_set_clk(struct clk *clk, uint hz) argument 504 rk3308_uart_get_clk(struct clk *clk) argument 556 rk3308_vop_get_clk(struct clk *clk) argument 592 rk3308_vop_set_clk(struct clk *clk, ulong hz) argument 924 rk3308_clk_get_rate(struct clk *clk) argument 1014 rk3308_clk_set_rate(struct clk *clk, ulong rate) argument 1098 rk3308_mac_set_parent(struct clk *clk, struct clk *parent) argument 1117 rk3308_clk_set_parent(struct clk *clk, struct clk *parent) argument [all...] |
/u-boot/drivers/clk/mtmips/ |
H A D | clk-mt7620.c | 8 #include <clk-uclass.h> 11 #include <dt-bindings/clock/mt7620-clk.h> 42 static ulong mt7620_clk_get_rate(struct clk *clk) argument 44 struct mt7620_clk_priv *priv = dev_get_priv(clk->dev); 46 if (clk->id >= ARRAY_SIZE(mt7620_clks)) 49 switch (mt7620_clks[clk->id]) { 61 return mt7620_clks[clk->id]; 88 static int mt7620_clk_enable(struct clk *clk) argument 98 mt7620_clk_disable(struct clk *clk) argument [all...] |
/u-boot/drivers/video/imx/ |
H A D | ipu.h | 22 struct clk { struct 25 /* Source clock this clk depends on */ 26 struct clk *parent; 28 struct clk *secondary; 42 void (*recalc) (struct clk *); 48 int (*set_rate) (struct clk *, unsigned long); 53 unsigned long (*round_rate) (struct clk *, unsigned long); 58 int (*enable) (struct clk *); 63 void (*disable) (struct clk *); 65 int (*set_parent) (struct clk *, struc [all...] |
/u-boot/board/samsung/smdkc100/ |
H A D | onenand.c | 21 struct s5pc100_clock *clk = local 30 value = readl(&clk->gate_d01); 33 writel(value, &clk->gate_d01); 35 value = readl(&clk->src0); 38 writel(value, &clk->src0); 40 value = readl(&clk->div1); 43 writel(value, &clk->div1);
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/u-boot/drivers/clk/ti/ |
H A D | clk-am3-dpll-x2.c | 7 * Loosely based on Linux kernel drivers/clk/ti/dpll.c 11 #include <clk-uclass.h> 14 #include <linux/clk-provider.h> 17 struct clk parent; 20 static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk) argument 22 struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(clk->dev); 30 dev_dbg(clk->dev, "rate=%ld\n", rate);
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/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
H A D | clk-bcm281xx.c | 16 #include <asm/kona-common/clk.h> 17 #include "clk-core.h" 25 .clk = { \ 43 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); 44 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); 45 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); 47 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); 48 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); 49 DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); 56 /* Lookup table for string to clk tranlatio [all...] |
H A D | clk-core.h | 26 struct clk; 31 struct clk *clk; member in struct:clk_lookup 47 * enable in struct clk. 51 int (*enable) (struct clk *c, int enable); 52 int (*set_rate) (struct clk *c, unsigned long rate); 53 unsigned long (*get_rate) (struct clk *c); 54 unsigned long (*round_rate) (struct clk *c, unsigned long rate); 55 int (*set_parent) (struct clk *c, struct clk *paren 58 struct clk { struct 411 struct clk clk; member in struct:refclk 415 struct clk clk; member in struct:peri_clock 420 struct clk clk; member in struct:ccu_clock 441 struct clk clk; member in struct:bus_clock 447 struct clk clk; member in struct:ref_clock [all...] |
/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
H A D | clk-bcm235xx.c | 16 #include <asm/kona-common/clk.h> 17 #include "clk-core.h" 25 .clk = { \ 43 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); 44 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); 45 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); 47 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); 48 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); 49 DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); 56 /* Lookup table for string to clk tranlatio [all...] |
H A D | clk-core.h | 26 struct clk; 31 struct clk *clk; member in struct:clk_lookup 47 * enable in struct clk. 51 int (*enable)(struct clk *c, int enable); 52 int (*set_rate)(struct clk *c, unsigned long rate); 53 unsigned long (*get_rate)(struct clk *c); 54 unsigned long (*round_rate)(struct clk *c, unsigned long rate); 55 int (*set_parent)(struct clk *c, struct clk *paren 58 struct clk { struct 411 struct clk clk; member in struct:refclk 415 struct clk clk; member in struct:peri_clock 420 struct clk clk; member in struct:ccu_clock 441 struct clk clk; member in struct:bus_clock 447 struct clk clk; member in struct:ref_clock [all...] |
/u-boot/drivers/cpu/ |
H A D | at91_cpu.c | 12 #include <linux/clk-provider.h> 80 struct clk clk; local 84 ret = clk_get_by_index(dev, 0, &clk); 88 rate = clk_get_rate(&clk); 93 ret = clk_get_by_index(dev, 1, &clk); 97 rate = clk_get_rate(&clk); 102 ret = clk_get_by_index(dev, 2, &clk); 106 rate = clk_get_rate(&clk);
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/u-boot/drivers/clk/exynos/ |
H A D | clk.c | 11 #include "clk.h" 20 struct clk *clk; local 25 clk = clk_register_mux(NULL, m->name, m->parent_names, 29 clk_dm(clk_id, clk); 40 struct clk *clk; local 45 clk = clk_register_divider(NULL, d->name, d->parent_name, 49 clk_dm(clk_id, clk); 60 struct clk *cl local [all...] |
H A D | clk-exynos7420.c | 11 #include <clk-uclass.h> 14 #include <dt-bindings/clock/exynos7420-clk.h> 90 static ulong exynos7420_topc_get_rate(struct clk *clk) argument 92 struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev); 94 switch (clk->id) { 116 struct clk in_clk; 145 static ulong exynos7420_top0_get_rate(struct clk *clk) argument 147 struct exynos7420_clk_top0_priv *priv = dev_get_priv(clk 193 exynos7420_peric1_get_rate(struct clk *clk) argument [all...] |
/u-boot/drivers/clk/at91/ |
H A D | clk-programmable.c | 9 * Based on drivers/clk/at91/clk-programmable.c from Linux. 12 #include <clk-uclass.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk/at91_pmc.h> 19 #define UBOOT_DM_CLK_AT91_PROG "at91-prog-clk" 33 struct clk clk; member in struct:clk_programmable 37 #define to_clk_programmable(_c) container_of(_c, struct clk_programmable, clk) 39 static ulong clk_programmable_get_rate(struct clk *cl argument 56 clk_programmable_set_parent(struct clk *clk, struct clk *parent) argument 88 clk_programmable_set_rate(struct clk *clk, ulong rate) argument 136 struct clk *clk; local [all...] |
H A D | clk-sam9x60-pll.c | 9 * Based on drivers/clk/at91/clk-sam9x60-pll.c from Linux. 15 #include <clk-uclass.h> 18 #include <linux/clk-provider.h> 19 #include <linux/clk/at91_pmc.h> 24 #define UBOOT_DM_CLK_AT91_SAM9X60_DIV_PLL "at91-sam9x60-div-pll-clk" 25 #define UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL "at91-sam9x60-frac-pll-clk" 44 struct clk clk; member in struct:sam9x60_pll 48 #define to_sam9x60_pll(_clk) container_of(_clk, struct sam9x60_pll, clk) 95 sam9x60_frac_pll_set_rate(struct clk *clk, ulong rate) argument 140 sam9x60_frac_pll_get_rate(struct clk *clk) argument 159 sam9x60_frac_pll_enable(struct clk *clk) argument 224 sam9x60_frac_pll_disable(struct clk *clk) argument 254 sam9x60_div_pll_enable(struct clk *clk) argument 284 sam9x60_div_pll_disable(struct clk *clk) argument 302 sam9x60_div_pll_set_rate(struct clk *clk, ulong rate) argument 343 sam9x60_div_pll_get_rate(struct clk *clk) argument 378 struct clk *clk; local [all...] |
/u-boot/drivers/mmc/ |
H A D | nexell_dw_mmc.c | 16 #include <asm/arch/clk.h> 38 struct clk *clk; member in struct:nexell_dwmmc_priv 52 struct clk *clk_get(const char *id); 97 struct clk *clk; local 104 clk = priv->clk; 105 if (!clk) { 107 clk 119 struct clk *clk; local [all...] |
/u-boot/arch/arm/include/asm/arch-imx8/ |
H A D | clock.h | 25 u32 mxc_get_clock(enum mxc_clock clk);
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/u-boot/arch/arm/include/asm/arch-mx27/ |
H A D | clock.h | 18 unsigned int mxc_get_clock(enum mxc_clock clk);
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/u-boot/arch/arm/mach-lpc32xx/ |
H A D | Makefile | 6 obj-y = cpu.o clk.o devices.o timer.o
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