1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2013 Broadcom Corporation. 4 */ 5 6#include <linux/stddef.h> 7#include <linux/stringify.h> 8 9#ifdef CONFIG_CLK_DEBUG 10#undef writel 11#undef readl 12static inline void writel(u32 val, void *addr) 13{ 14 printf("Write [0x%p] = 0x%08x\n", addr, val); 15 *(u32 *)addr = val; 16} 17 18static inline u32 readl(void *addr) 19{ 20 u32 val = *(u32 *)addr; 21 printf("Read [0x%p] = 0x%08x\n", addr, val); 22 return val; 23} 24#endif 25 26struct clk; 27 28struct clk_lookup { 29 const char *dev_id; 30 const char *con_id; 31 struct clk *clk; 32}; 33 34extern struct clk_lookup arch_clk_tbl[]; 35extern unsigned int arch_clk_tbl_array_size; 36 37/** 38 * struct clk_ops - standard clock operations 39 * @enable: enable/disable clock, see clk_enable() and clk_disable() 40 * @set_rate: set the clock rate, see clk_set_rate(). 41 * @get_rate: get the clock rate, see clk_get_rate(). 42 * @round_rate: round a given clock rate, see clk_round_rate(). 43 * @set_parent: set the clock's parent, see clk_set_parent(). 44 * 45 * Group the common clock implementations together so that we 46 * don't have to keep setting the same fiels again. We leave 47 * enable in struct clk. 48 * 49 */ 50struct clk_ops { 51 int (*enable)(struct clk *c, int enable); 52 int (*set_rate)(struct clk *c, unsigned long rate); 53 unsigned long (*get_rate)(struct clk *c); 54 unsigned long (*round_rate)(struct clk *c, unsigned long rate); 55 int (*set_parent)(struct clk *c, struct clk *parent); 56}; 57 58struct clk { 59 struct clk *parent; 60 const char *name; 61 int use_cnt; 62 unsigned long rate; /* in HZ */ 63 64 /* programmable divider. 0 means fixed ratio to parent clock */ 65 unsigned long div; 66 67 struct clk_src *src; 68 struct clk_ops *ops; 69 70 unsigned long ccu_clk_mgr_base; 71 int sel; 72}; 73 74struct refclk *refclk_str_to_clk(const char *name); 75 76/* The common clock framework uses u8 to represent a parent index */ 77#define PARENT_COUNT_MAX ((u32)U8_MAX) 78 79#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ 80#define BAD_CLK_NAME ((const char *)-1) 81 82#define BAD_SCALED_DIV_VALUE U64_MAX 83 84/* 85 * Utility macros for object flag management. If possible, flags 86 * should be defined such that 0 is the desired default value. 87 */ 88#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag 89#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) 90#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) 91#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) 92#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) 93 94/* Clock field state tests */ 95 96#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) 97#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) 98#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) 99#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) 100#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) 101#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) 102 103#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) 104 105#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) 106#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) 107#define divider_has_fraction(div) (!divider_is_fixed(div) && \ 108 (div)->frac_width > 0) 109 110#define selector_exists(sel) ((sel)->width != 0) 111#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) 112 113/* Clock type, used to tell common block what it's part of */ 114enum bcm_clk_type { 115 bcm_clk_none, /* undefined clock type */ 116 bcm_clk_bus, 117 bcm_clk_core, 118 bcm_clk_peri 119}; 120 121/* 122 * Gating control and status is managed by a 32-bit gate register. 123 * 124 * There are several types of gating available: 125 * - (no gate) 126 * A clock with no gate is assumed to be always enabled. 127 * - hardware-only gating (auto-gating) 128 * Enabling or disabling clocks with this type of gate is 129 * managed automatically by the hardware. Such clocks can be 130 * considered by the software to be enabled. The current status 131 * of auto-gated clocks can be read from the gate status bit. 132 * - software-only gating 133 * Auto-gating is not available for this type of clock. 134 * Instead, software manages whether it's enabled by setting or 135 * clearing the enable bit. The current gate status of a gate 136 * under software control can be read from the gate status bit. 137 * To ensure a change to the gating status is complete, the 138 * status bit can be polled to verify that the gate has entered 139 * the desired state. 140 * - selectable hardware or software gating 141 * Gating for this type of clock can be configured to be either 142 * under software or hardware control. Which type is in use is 143 * determined by the hw_sw_sel bit of the gate register. 144 */ 145struct bcm_clk_gate { 146 u32 offset; /* gate register offset */ 147 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ 148 u32 en_bit; /* 0: disable; 1: enable */ 149 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ 150 u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ 151}; 152 153/* 154 * Gate flags: 155 * HW means this gate can be auto-gated 156 * SW means the state of this gate can be software controlled 157 * NO_DISABLE means this gate is (only) enabled if under software control 158 * SW_MANAGED means the status of this gate is under software control 159 * ENABLED means this software-managed gate is *supposed* to be enabled 160 */ 161#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ 162#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ 163#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ 164#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ 165#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ 166#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ 167 168/* 169 * Gate initialization macros. 170 * 171 * Any gate initially under software control will be enabled. 172 */ 173 174/* A hardware/software gate initially under software control */ 175#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 176 { \ 177 .offset = (_offset), \ 178 .status_bit = (_status_bit), \ 179 .en_bit = (_en_bit), \ 180 .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 181 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 182 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ 183 FLAG(GATE, EXISTS), \ 184 } 185 186/* A hardware/software gate initially under hardware control */ 187#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 188 { \ 189 .offset = (_offset), \ 190 .status_bit = (_status_bit), \ 191 .en_bit = (_en_bit), \ 192 .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 193 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 194 FLAG(GATE, EXISTS), \ 195 } 196 197/* A hardware-or-enabled gate (enabled if not under hardware control) */ 198#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 199 { \ 200 .offset = (_offset), \ 201 .status_bit = (_status_bit), \ 202 .en_bit = (_en_bit), \ 203 .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 204 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 205 FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ 206 } 207 208/* A software-only gate */ 209#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ 210 { \ 211 .offset = (_offset), \ 212 .status_bit = (_status_bit), \ 213 .en_bit = (_en_bit), \ 214 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ 215 FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ 216 } 217 218/* A hardware-only gate */ 219#define HW_ONLY_GATE(_offset, _status_bit) \ 220 { \ 221 .offset = (_offset), \ 222 .status_bit = (_status_bit), \ 223 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ 224 } 225 226/* 227 * Each clock can have zero, one, or two dividers which change the 228 * output rate of the clock. Each divider can be either fixed or 229 * variable. If there are two dividers, they are the "pre-divider" 230 * and the "regular" or "downstream" divider. If there is only one, 231 * there is no pre-divider. 232 * 233 * A fixed divider is any non-zero (positive) value, and it 234 * indicates how the input rate is affected by the divider. 235 * 236 * The value of a variable divider is maintained in a sub-field of a 237 * 32-bit divider register. The position of the field in the 238 * register is defined by its offset and width. The value recorded 239 * in this field is always 1 less than the value it represents. 240 * 241 * In addition, a variable divider can indicate that some subset 242 * of its bits represent a "fractional" part of the divider. Such 243 * bits comprise the low-order portion of the divider field, and can 244 * be viewed as representing the portion of the divider that lies to 245 * the right of the decimal point. Most variable dividers have zero 246 * fractional bits. Variable dividers with non-zero fraction width 247 * still record a value 1 less than the value they represent; the 248 * added 1 does *not* affect the low-order bit in this case, it 249 * affects the bits above the fractional part only. (Often in this 250 * code a divider field value is distinguished from the value it 251 * represents by referring to the latter as a "divisor".) 252 * 253 * In order to avoid dealing with fractions, divider arithmetic is 254 * performed using "scaled" values. A scaled value is one that's 255 * been left-shifted by the fractional width of a divider. Dividing 256 * a scaled value by a scaled divisor produces the desired quotient 257 * without loss of precision and without any other special handling 258 * for fractions. 259 * 260 * The recorded value of a variable divider can be modified. To 261 * modify either divider (or both), a clock must be enabled (i.e., 262 * using its gate). In addition, a trigger register (described 263 * below) must be used to commit the change, and polled to verify 264 * the change is complete. 265 */ 266struct bcm_clk_div { 267 union { 268 struct { /* variable divider */ 269 u32 offset; /* divider register offset */ 270 u32 shift; /* field shift */ 271 u32 width; /* field width */ 272 u32 frac_width; /* field fraction width */ 273 274 u64 scaled_div; /* scaled divider value */ 275 }; 276 u32 fixed; /* non-zero fixed divider value */ 277 }; 278 u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ 279}; 280 281/* 282 * Divider flags: 283 * EXISTS means this divider exists 284 * FIXED means it is a fixed-rate divider 285 */ 286#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ 287#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ 288 289/* Divider initialization macros */ 290 291/* A fixed (non-zero) divider */ 292#define FIXED_DIVIDER(_value) \ 293 { \ 294 .fixed = (_value), \ 295 .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ 296 } 297 298/* A divider with an integral divisor */ 299#define DIVIDER(_offset, _shift, _width) \ 300 { \ 301 .offset = (_offset), \ 302 .shift = (_shift), \ 303 .width = (_width), \ 304 .scaled_div = BAD_SCALED_DIV_VALUE, \ 305 .flags = FLAG(DIV, EXISTS), \ 306 } 307 308/* A divider whose divisor has an integer and fractional part */ 309#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ 310 { \ 311 .offset = (_offset), \ 312 .shift = (_shift), \ 313 .width = (_width), \ 314 .frac_width = (_frac_width), \ 315 .scaled_div = BAD_SCALED_DIV_VALUE, \ 316 .flags = FLAG(DIV, EXISTS), \ 317 } 318 319/* 320 * Clocks may have multiple "parent" clocks. If there is more than 321 * one, a selector must be specified to define which of the parent 322 * clocks is currently in use. The selected clock is indicated in a 323 * sub-field of a 32-bit selector register. The range of 324 * representable selector values typically exceeds the number of 325 * available parent clocks. Occasionally the reset value of a 326 * selector field is explicitly set to a (specific) value that does 327 * not correspond to a defined input clock. 328 * 329 * We register all known parent clocks with the common clock code 330 * using a packed array (i.e., no empty slots) of (parent) clock 331 * names, and refer to them later using indexes into that array. 332 * We maintain an array of selector values indexed by common clock 333 * index values in order to map between these common clock indexes 334 * and the selector values used by the hardware. 335 * 336 * Like dividers, a selector can be modified, but to do so a clock 337 * must be enabled, and a trigger must be used to commit the change. 338 */ 339struct bcm_clk_sel { 340 u32 offset; /* selector register offset */ 341 u32 shift; /* field shift */ 342 u32 width; /* field width */ 343 344 u32 parent_count; /* number of entries in parent_sel[] */ 345 u32 *parent_sel; /* array of parent selector values */ 346 u8 clk_index; /* current selected index in parent_sel[] */ 347}; 348 349/* Selector initialization macro */ 350#define SELECTOR(_offset, _shift, _width) \ 351 { \ 352 .offset = (_offset), \ 353 .shift = (_shift), \ 354 .width = (_width), \ 355 .clk_index = BAD_CLK_INDEX, \ 356 } 357 358/* 359 * Making changes to a variable divider or a selector for a clock 360 * requires the use of a trigger. A trigger is defined by a single 361 * bit within a register. To signal a change, a 1 is written into 362 * that bit. To determine when the change has been completed, that 363 * trigger bit is polled; the read value will be 1 while the change 364 * is in progress, and 0 when it is complete. 365 * 366 * Occasionally a clock will have more than one trigger. In this 367 * case, the "pre-trigger" will be used when changing a clock's 368 * selector and/or its pre-divider. 369 */ 370struct bcm_clk_trig { 371 u32 offset; /* trigger register offset */ 372 u32 bit; /* trigger bit */ 373 u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ 374}; 375 376/* 377 * Trigger flags: 378 * EXISTS means this trigger exists 379 */ 380#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ 381 382/* Trigger initialization macro */ 383#define TRIGGER(_offset, _bit) \ 384 { \ 385 .offset = (_offset), \ 386 .bit = (_bit), \ 387 .flags = FLAG(TRIG, EXISTS), \ 388 } 389 390struct bus_clk_data { 391 struct bcm_clk_gate gate; 392}; 393 394struct core_clk_data { 395 struct bcm_clk_gate gate; 396}; 397 398struct peri_clk_data { 399 struct bcm_clk_gate gate; 400 struct bcm_clk_trig pre_trig; 401 struct bcm_clk_div pre_div; 402 struct bcm_clk_trig trig; 403 struct bcm_clk_div div; 404 struct bcm_clk_sel sel; 405 const char *clocks[]; /* must be last; use CLOCKS() to declare */ 406}; 407#define CLOCKS(...) { __VA_ARGS__, NULL, } 408#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ 409 410struct refclk { 411 struct clk clk; 412}; 413 414struct peri_clock { 415 struct clk clk; 416 struct peri_clk_data *data; 417}; 418 419struct ccu_clock { 420 struct clk clk; 421 422 int num_policy_masks; 423 unsigned long policy_freq_offset; 424 int freq_bit_shift; /* 8 for most CCUs */ 425 unsigned long policy_ctl_offset; 426 unsigned long policy0_mask_offset; 427 unsigned long policy1_mask_offset; 428 unsigned long policy2_mask_offset; 429 unsigned long policy3_mask_offset; 430 unsigned long policy0_mask2_offset; 431 unsigned long policy1_mask2_offset; 432 unsigned long policy2_mask2_offset; 433 unsigned long policy3_mask2_offset; 434 unsigned long lvm_en_offset; 435 436 int freq_id; 437 unsigned long *freq_tbl; 438}; 439 440struct bus_clock { 441 struct clk clk; 442 struct bus_clk_data *data; 443 unsigned long *freq_tbl; 444}; 445 446struct ref_clock { 447 struct clk clk; 448}; 449 450static inline int is_same_clock(struct clk *a, struct clk *b) 451{ 452 return a == b; 453} 454 455#define to_clk(p) (&((p)->clk)) 456#define name_to_clk(name) (&((name##_clk).clk)) 457/* declare a struct clk_lookup */ 458#define CLK_LK(name) \ 459{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),} 460 461static inline struct refclk *to_refclk(struct clk *clock) 462{ 463 return container_of(clock, struct refclk, clk); 464} 465 466static inline struct peri_clock *to_peri_clk(struct clk *clock) 467{ 468 return container_of(clock, struct peri_clock, clk); 469} 470 471static inline struct ccu_clock *to_ccu_clk(struct clk *clock) 472{ 473 return container_of(clock, struct ccu_clock, clk); 474} 475 476static inline struct bus_clock *to_bus_clk(struct clk *clock) 477{ 478 return container_of(clock, struct bus_clock, clk); 479} 480 481static inline struct ref_clock *to_ref_clk(struct clk *clock) 482{ 483 return container_of(clock, struct ref_clock, clk); 484} 485 486extern struct clk_ops peri_clk_ops; 487extern struct clk_ops ccu_clk_ops; 488extern struct clk_ops bus_clk_ops; 489extern struct clk_ops ref_clk_ops; 490 491int clk_get_and_enable(char *clkstr); 492